Report time       : 2018. máj. 30., szerda, 11.45.30 CEST.
Solution          : axi_port_only.
Simulation tool   : xsim.

+----------+----------+-----------------------------------------------+-----------------------------------------------+
|          |          |                    Latency                    |                    Interval                   |
+   RTL    +  Status  +-----------------------------------------------+-----------------------------------------------+
|          |          |      min      |      avg      |      max      |      min      |      avg      |      max      |
+----------+----------+-----------------------------------------------+-----------------------------------------------+
|      VHDL|      Pass|            485|            485|            485|             NA|             NA|             NA|
|   Verilog|        NA|             NA|             NA|             NA|             NA|             NA|             NA|
+----------+----------+-----------------------------------------------+-----------------------------------------------+