================================================================
== Vivado HLS Report for 'write_pixel'
================================================================
* Date:           Wed May 30 11:44:02 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       axi_port_only
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.75|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |  332|  332|  332|  332|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +--------------+-----+-----+----------+-----------+-----------+------+----------+
        |              |  Latency  | Iteration|  Initiation Interval  | Trip |          |
        |   Loop Name  | min | max |  Latency |  achieved |   target  | Count| Pipelined|
        +--------------+-----+-----+----------+-----------+-----------+------+----------+
        |- write_loop  |  325|  325|         3|          1|          1|   324|    yes   |
        +--------------+-----+-----+----------+-----------+-----------+------+----------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 0
ResetActiveHigh: 1
IsCombinational: 2
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 1, depth = 3


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 10
* Pipeline : 1
  Pipeline-0 : II = 1, D = 3, States = { 3 4 5 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	6  / (exitcond_i)
	4  / (!exitcond_i)
4 --> 
	5  / true
5 --> 
	3  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	10  / true
10 --> 

* FSM state operations: 

 <State 1> : 3.63ns
ST_1 : Operation 11 [1/1] (3.63ns)   --->   "%out_array_offset_rea = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %out_array_offset)"   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_1 : Operation 12 [1/1] (0.00ns)   --->   "%out_array_offset1_i = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %out_array_offset_rea, i32 2, i32 31)"

 <State 2> : 8.75ns
ST_2 : Operation 13 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str44, i32 0, i32 0, [1 x i8]* @p_str45, [1 x i8]* @p_str46, [1 x i8]* @p_str47, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str48, [1 x i8]* @p_str49)"
ST_2 : Operation 14 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [10 x i8]* @p_str10, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 15 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %out_array_offset, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str29, i32 0, i32 0, [1 x i8]* @p_str30, [1 x i8]* @p_str31, [1 x i8]* @p_str32, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str33, [1 x i8]* @p_str34)"
ST_2 : Operation 16 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str44, i32 0, i32 0, [1 x i8]* @p_str45, [1 x i8]* @p_str46, [1 x i8]* @p_str47, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str48, [1 x i8]* @p_str49)"
ST_2 : Operation 17 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [10 x i8]* @p_str10, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_2 : Operation 18 [1/1] (0.00ns)   --->   "%sext_i = zext i30 %out_array_offset1_i to i64"
ST_2 : Operation 19 [1/1] (0.00ns)   --->   "%out_array_addr = getelementptr float* %out_array, i64 %sext_i"
ST_2 : Operation 20 [1/1] (8.75ns)   --->   "%out_array_addr_i_wr_s = call i1 @_ssdm_op_WriteReq.m_axi.floatP(float* %out_array_addr, i32 324)" [edge_detection/edge_detection.cpp:42]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_2 : Operation 21 [1/1] (1.76ns)   --->   "br label %0" [edge_detection/edge_detection.cpp:39]

 <State 3> : 1.94ns
ST_3 : Operation 22 [1/1] (0.00ns)   --->   "%i_i = phi i9 [ 0, %entry ], [ %i, %1 ]"
ST_3 : Operation 23 [1/1] (1.66ns)   --->   "%exitcond_i = icmp eq i9 %i_i, -188" [edge_detection/edge_detection.cpp:39]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.66> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 24 [1/1] (1.93ns)   --->   "%i = add i9 %i_i, 1" [edge_detection/edge_detection.cpp:39]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.93> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 25 [1/1] (0.00ns)   --->   "br i1 %exitcond_i, label %.exit, label %1" [edge_detection/edge_detection.cpp:39]

 <State 4> : 3.63ns
ST_4 : Operation 26 [1/1] (3.63ns)   --->   "%tmp = call float @_ssdm_op_Read.ap_fifo.volatile.floatP(float* %out_stream_V)" [edge_detection/edge_detection.cpp:41]   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>

 <State 5> : 8.75ns
ST_5 : Operation 27 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 324, i64 324, i64 324)"
ST_5 : Operation 28 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecLoopName([11 x i8]* @p_str2) nounwind" [edge_detection/edge_detection.cpp:39]
ST_5 : Operation 29 [1/1] (0.00ns)   --->   "%tmp_2_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([11 x i8]* @p_str2)" [edge_detection/edge_detection.cpp:39]
ST_5 : Operation 30 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:40]
ST_5 : Operation 31 [1/1] (8.75ns)   --->   "call void @_ssdm_op_Write.m_axi.floatP(float* %out_array_addr, float %tmp, i4 -1)" [edge_detection/edge_detection.cpp:42]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_5 : Operation 32 [1/1] (0.00ns)   --->   "%empty_9 = call i32 (...)* @_ssdm_op_SpecRegionEnd([11 x i8]* @p_str2, i32 %tmp_2_i)" [edge_detection/edge_detection.cpp:43]
ST_5 : Operation 33 [1/1] (0.00ns)   --->   "br label %0" [edge_detection/edge_detection.cpp:39]

 <State 6> : 8.75ns
ST_6 : Operation 34 [5/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:42]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 7> : 8.75ns
ST_7 : Operation 35 [4/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:42]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 8> : 8.75ns
ST_8 : Operation 36 [3/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:42]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 9> : 8.75ns
ST_9 : Operation 37 [2/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:42]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 10> : 8.75ns
ST_10 : Operation 38 [1/5] (8.75ns)   --->   "%out_array_addr_i_wr_1 = call i1 @_ssdm_op_WriteResp.m_axi.floatP(float* %out_array_addr)" [edge_detection/edge_detection.cpp:42]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_10 : Operation 39 [1/1] (0.00ns)   --->   "ret void"


============================================================
+ Verbose Summary: Timing violations
============================================================
Target clock period: 10ns, clock uncertainty: 1.25ns.

 <State 1>: 3.63ns
The critical path consists of the following:
	fifo read on port 'out_array_offset' [7]  (3.63 ns)

 <State 2>: 8.75ns
The critical path consists of the following:
	'getelementptr' operation ('out_array_addr') [12]  (0 ns)
	bus request on port 'out_array' (edge_detection/edge_detection.cpp:42) [13]  (8.75 ns)

 <State 3>: 1.94ns
The critical path consists of the following:
	'phi' operation ('i') with incoming values : ('i', edge_detection/edge_detection.cpp:39) [16]  (0 ns)
	'add' operation ('i', edge_detection/edge_detection.cpp:39) [18]  (1.94 ns)

 <State 4>: 3.63ns
The critical path consists of the following:
	fifo read on port 'out_stream_V' (edge_detection/edge_detection.cpp:41) [25]  (3.63 ns)

 <State 5>: 8.75ns
The critical path consists of the following:
	bus write on port 'out_array' (edge_detection/edge_detection.cpp:42) [26]  (8.75 ns)

 <State 6>: 8.75ns
The critical path consists of the following:
	bus access on port 'out_array' (edge_detection/edge_detection.cpp:42) [30]  (8.75 ns)

 <State 7>: 8.75ns
The critical path consists of the following:
	bus access on port 'out_array' (edge_detection/edge_detection.cpp:42) [30]  (8.75 ns)

 <State 8>: 8.75ns
The critical path consists of the following:
	bus access on port 'out_array' (edge_detection/edge_detection.cpp:42) [30]  (8.75 ns)

 <State 9>: 8.75ns
The critical path consists of the following:
	bus access on port 'out_array' (edge_detection/edge_detection.cpp:42) [30]  (8.75 ns)

 <State 10>: 8.75ns
The critical path consists of the following:
	bus access on port 'out_array' (edge_detection/edge_detection.cpp:42) [30]  (8.75 ns)


============================================================
+ Verbose Summary: Binding
============================================================
N/A
* FSMD analyzer results:
  - Output states:
 - Input state : 
  - Chain level:
	State 1
	State 2
	State 3
	State 4
	State 5
	State 6
	State 7
	State 8
	State 9
	State 10


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================
N/A