================================================================ == Vivado HLS Report for 'read_pixel13' ================================================================ * Date: Wed May 30 11:44:03 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: axi_port_only * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+---------+ | Latency | Interval | Pipeline| | min | max | min | max | Type | +-----+-----+-----+-----+---------+ | 409| 409| 409| 409| none | +-----+-----+-----+-----+---------+ + Detail: * Instance: N/A * Loop: +-------------+-----+-----+----------+-----------+-----------+------+----------+ | | Latency | Iteration| Initiation Interval | Trip | | | Loop Name | min | max | Latency | achieved | target | Count| Pipelined| +-------------+-----+-----+----------+-----------+-----------+------+----------+ |- read_loop | 401| 401| 3| 1| 1| 400| yes | +-------------+-----+-----+----------+-----------+-----------+------+----------+ ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| -| 0| 85| |FIFO | -| -| -| -| |Instance | -| -| -| -| |Memory | -| -| -| -| |Multiplexer | -| -| -| 137| |Register | -| -| 58| -| +-----------------+---------+-------+--------+-------+ |Total | 0| 0| 58| 222| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 0| 0| ~0 | ~0 | +-----------------+---------+-------+--------+-------+ + Detail: * Instance: N/A * DSP48: N/A * Memory: N/A * FIFO: N/A * Expression: +-----------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +-----------------------------------+----------+-------+---+----+------------+------------+ |i_fu_169_p2 | + | 0| 0| 16| 9| 1| |ap_block_state10_pp0_stage0_iter2 | and | 0| 0| 8| 1| 1| |ap_block_state9_pp0_stage0_iter1 | and | 0| 0| 8| 1| 1| |ap_condition_298 | and | 0| 0| 8| 1| 1| |exitcond_i_i_fu_163_p2 | icmp | 0| 0| 13| 9| 8| |ap_block_pp0_stage0_01001 | or | 0| 0| 8| 1| 1| |ap_block_state1 | or | 0| 0| 8| 1| 1| |ap_enable_pp0 | xor | 0| 0| 8| 1| 2| |ap_enable_reg_pp0_iter1 | xor | 0| 0| 8| 2| 1| +-----------------------------------+----------+-------+---+----+------------+------------+ |Total | | 0| 0| 85| 26| 17| +-----------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: +---------------------------------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +---------------------------------------+----+-----------+-----+-----------+ |ap_NS_fsm | 47| 10| 1| 10| |ap_done | 9| 2| 1| 2| |ap_enable_reg_pp0_iter1 | 9| 2| 1| 2| |ap_enable_reg_pp0_iter2 | 9| 2| 1| 2| |ap_sig_ioackin_m_axi_in_array_ARREADY | 9| 2| 1| 2| |i_i_i_reg_131 | 9| 2| 9| 18| |in_array_blk_n_AR | 9| 2| 1| 2| |in_array_blk_n_R | 9| 2| 1| 2| |in_stream_V_blk_n | 9| 2| 1| 2| |out_array_offset_out_blk_n | 9| 2| 1| 2| |real_start | 9| 2| 1| 2| +---------------------------------------+----+-----------+-----+-----------+ |Total | 137| 30| 19| 46| +---------------------------------------+----+-----------+-----+-----------+ * Register: +---------------------------------------+----+----+-----+-----------+ | Name | FF | LUT| Bits| Const Bits| +---------------------------------------+----+----+-----+-----------+ |ap_CS_fsm | 9| 0| 9| 0| |ap_done_reg | 1| 0| 1| 0| |ap_enable_reg_pp0_iter0 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter1 | 1| 0| 1| 0| |ap_enable_reg_pp0_iter2 | 1| 0| 1| 0| |ap_reg_ioackin_m_axi_in_array_ARREADY | 1| 0| 1| 0| |ap_reg_pp0_iter1_exitcond_i_i_reg_181 | 1| 0| 1| 0| |exitcond_i_i_reg_181 | 1| 0| 1| 0| |i_i_i_reg_131 | 9| 0| 9| 0| |start_once_reg | 1| 0| 1| 0| |temp_reg_190 | 32| 0| 32| 0| +---------------------------------------+----+----+-----+-----------+ |Total | 58| 0| 58| 0| +---------------------------------------+----+----+-----+-----------+ ================================================================ == Interface ================================================================ * Summary: +-----------------------------+-----+-----+------------+----------------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object | C Type | +-----------------------------+-----+-----+------------+----------------------+--------------+ |ap_clk | in | 1| ap_ctrl_hs | read_pixel13 | return value | |ap_rst | in | 1| ap_ctrl_hs | read_pixel13 | return value | |ap_start | in | 1| ap_ctrl_hs | read_pixel13 | return value | |start_full_n | in | 1| ap_ctrl_hs | read_pixel13 | return value | |ap_done | out | 1| ap_ctrl_hs | read_pixel13 | return value | |ap_continue | in | 1| ap_ctrl_hs | read_pixel13 | return value | |ap_idle | out | 1| ap_ctrl_hs | read_pixel13 | return value | |ap_ready | out | 1| ap_ctrl_hs | read_pixel13 | return value | |start_out | out | 1| ap_ctrl_hs | read_pixel13 | return value | |start_write | out | 1| ap_ctrl_hs | read_pixel13 | return value | |in_stream_V_din | out | 32| ap_fifo | in_stream_V | pointer | |in_stream_V_full_n | in | 1| ap_fifo | in_stream_V | pointer | |in_stream_V_write | out | 1| ap_fifo | in_stream_V | pointer | |m_axi_in_array_AWVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_AWREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_AWADDR | out | 32| m_axi | in_array | pointer | |m_axi_in_array_AWID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_AWLEN | out | 32| m_axi | in_array | pointer | |m_axi_in_array_AWSIZE | out | 3| m_axi | in_array | pointer | |m_axi_in_array_AWBURST | out | 2| m_axi | in_array | pointer | |m_axi_in_array_AWLOCK | out | 2| m_axi | in_array | pointer | |m_axi_in_array_AWCACHE | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWPROT | out | 3| m_axi | in_array | pointer | |m_axi_in_array_AWQOS | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWREGION | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_WDATA | out | 32| m_axi | in_array | pointer | |m_axi_in_array_WSTRB | out | 4| m_axi | in_array | pointer | |m_axi_in_array_WLAST | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_ARADDR | out | 32| m_axi | in_array | pointer | |m_axi_in_array_ARID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARLEN | out | 32| m_axi | in_array | pointer | |m_axi_in_array_ARSIZE | out | 3| m_axi | in_array | pointer | |m_axi_in_array_ARBURST | out | 2| m_axi | in_array | pointer | |m_axi_in_array_ARLOCK | out | 2| m_axi | in_array | pointer | |m_axi_in_array_ARCACHE | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARPROT | out | 3| m_axi | in_array | pointer | |m_axi_in_array_ARQOS | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARREGION | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_RVALID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RREADY | out | 1| m_axi | in_array | pointer | |m_axi_in_array_RDATA | in | 32| m_axi | in_array | pointer | |m_axi_in_array_RLAST | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RUSER | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RRESP | in | 2| m_axi | in_array | pointer | |m_axi_in_array_BVALID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_BREADY | out | 1| m_axi | in_array | pointer | |m_axi_in_array_BRESP | in | 2| m_axi | in_array | pointer | |m_axi_in_array_BID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_BUSER | in | 1| m_axi | in_array | pointer | |in_array_offset | in | 32| ap_none | in_array_offset | scalar | |out_array_offset | in | 32| ap_none | out_array_offset | scalar | |out_array_offset_out_din | out | 32| ap_fifo | out_array_offset_out | pointer | |out_array_offset_out_full_n | in | 1| ap_fifo | out_array_offset_out | pointer | |out_array_offset_out_write | out | 1| ap_fifo | out_array_offset_out | pointer | +-----------------------------+-----+-----+------------+----------------------+--------------+ ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 0 ResetActiveHigh: 1 IsCombinational: 2 IsDatapathOnly: 0 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 + Individual pipeline summary: * Pipeline-0: initiation interval (II) = 1, depth = 3 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 11 * Pipeline : 1 Pipeline-0 : II = 1, D = 3, States = { 8 9 10 } * Dataflow Pipeline: 0 * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> 7 / true 7 --> 8 / true 8 --> 11 / (exitcond_i_i) 9 / (!exitcond_i_i) 9 --> 10 / true 10 --> 8 / true 11 --> * FSM state operations: : 8.75ns ST_1 : Operation 12 [1/1] (0.00ns) ---> "%in_array_offset_read = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %in_array_offset)" ST_1 : Operation 13 [1/1] (0.00ns) ---> "%in_array_offset1_i_i = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %in_array_offset_read, i32 2, i32 31)" ST_1 : Operation 14 [1/1] (0.00ns) ---> "%sext_i_i = zext i30 %in_array_offset1_i_i to i64" ST_1 : Operation 15 [1/1] (0.00ns) ---> "%in_array_addr = getelementptr float* %in_array, i64 %sext_i_i" ST_1 : Operation 16 [7/7] (8.75ns) ---> "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15] ---> Core 9 'm_axi' : 8.75ns ST_2 : Operation 17 [6/7] (8.75ns) ---> "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15] ---> Core 9 'm_axi' : 8.75ns ST_3 : Operation 18 [5/7] (8.75ns) ---> "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15] ---> Core 9 'm_axi' : 8.75ns ST_4 : Operation 19 [4/7] (8.75ns) ---> "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15] ---> Core 9 'm_axi' : 8.75ns ST_5 : Operation 20 [3/7] (8.75ns) ---> "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15] ---> Core 9 'm_axi' : 8.75ns ST_6 : Operation 21 [2/7] (8.75ns) ---> "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15] ---> Core 9 'm_axi' : 8.75ns ST_7 : Operation 22 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)" ST_7 : Operation 23 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)" ST_7 : Operation 24 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_7 : Operation 25 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_7 : Operation 26 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32* %out_array_offset_out, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str15, i32 0, i32 0, [1 x i8]* @p_str16, [1 x i8]* @p_str17, [1 x i8]* @p_str18, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str19, [1 x i8]* @p_str20)" ST_7 : Operation 27 [1/1] (0.00ns) ---> "%out_array_offset_rea = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %out_array_offset)" ST_7 : Operation 28 [1/1] (3.63ns) ---> "call void @_ssdm_op_Write.ap_fifo.i32P(i32* %out_array_offset_out, i32 %out_array_offset_rea)" ---> Core 32 'FIFO' ST_7 : Operation 29 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)" ST_7 : Operation 30 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_7 : Operation 31 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)" ST_7 : Operation 32 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_7 : Operation 33 [1/7] (8.75ns) ---> "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15] ---> Core 9 'm_axi' ST_7 : Operation 34 [1/1] (1.76ns) ---> "br label %0" [edge_detection/edge_detection.cpp:14] : 1.94ns ST_8 : Operation 35 [1/1] (0.00ns) ---> "%i_i_i = phi i9 [ 0, %entry ], [ %i, %1 ]" ST_8 : Operation 36 [1/1] (1.66ns) ---> "%exitcond_i_i = icmp eq i9 %i_i_i, -112" [edge_detection/edge_detection.cpp:14] ---> Core 25 'Cmp' ST_8 : Operation 37 [1/1] (1.93ns) ---> "%i = add i9 %i_i_i, 1" [edge_detection/edge_detection.cpp:14] ---> Core 14 'AddSub' ST_8 : Operation 38 [1/1] (0.00ns) ---> "br i1 %exitcond_i_i, label %.exit, label %1" [edge_detection/edge_detection.cpp:14] : 8.75ns ST_9 : Operation 39 [1/1] (8.75ns) ---> "%temp = call float @_ssdm_op_Read.m_axi.floatP(float* %in_array_addr)" [edge_detection/edge_detection.cpp:15] ---> Core 9 'm_axi' : 3.63ns ST_10 : Operation 40 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 400, i64 400, i64 400)" ST_10 : Operation 41 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecLoopName([10 x i8]* @p_str) nounwind" [edge_detection/edge_detection.cpp:14] ST_10 : Operation 42 [1/1] (0.00ns) ---> "%tmp_3_i_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([10 x i8]* @p_str)" [edge_detection/edge_detection.cpp:14] ST_10 : Operation 43 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:15] ST_10 : Operation 44 [1/1] (3.63ns) ---> "call void @_ssdm_op_Write.ap_fifo.volatile.floatP(float* %in_stream_V, float %temp)" [edge_detection/edge_detection.cpp:16] ---> Core 32 'FIFO' ST_10 : Operation 45 [1/1] (0.00ns) ---> "%empty_10 = call i32 (...)* @_ssdm_op_SpecRegionEnd([10 x i8]* @p_str, i32 %tmp_3_i_i)" [edge_detection/edge_detection.cpp:17] ST_10 : Operation 46 [1/1] (0.00ns) ---> "br label %0" [edge_detection/edge_detection.cpp:14] : 0.00ns ST_11 : Operation 47 [1/1] (0.00ns) ---> "ret void" ============================================================ + Verbose Summary: Binding ============================================================ STG Binding: ---------------- STG Properties BEGIN ---------------- - Is combinational: 0 - Is one-state seq: 0 - Is datapath-only: 0 - Is pipelined: 0 - Is top level: 0 Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0 Port [ in_stream_V]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0 Port [ in_array]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0 Port [ in_array_offset]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ out_array_offset]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ out_array_offset_out]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0 ---------------- STG Properties END ------------------ ---------------- Datapath Model BEGIN ---------------- in_array_offset_read (read ) [ 000000000000] in_array_offset1_i_i (partselect ) [ 000000000000] sext_i_i (zext ) [ 000000000000] in_array_addr (getelementptr ) [ 001111111110] StgValue_22 (specinterface ) [ 000000000000] StgValue_23 (specinterface ) [ 000000000000] StgValue_24 (specinterface ) [ 000000000000] StgValue_25 (specinterface ) [ 000000000000] StgValue_26 (specinterface ) [ 000000000000] out_array_offset_rea (read ) [ 000000000000] StgValue_28 (write ) [ 000000000000] StgValue_29 (specinterface ) [ 000000000000] StgValue_30 (specinterface ) [ 000000000000] StgValue_31 (specinterface ) [ 000000000000] StgValue_32 (specinterface ) [ 000000000000] in_array_addr_i_i_rd (readreq ) [ 000000000000] StgValue_34 (br ) [ 000000011110] i_i_i (phi ) [ 000000001000] exitcond_i_i (icmp ) [ 000000001110] i (add ) [ 000000011110] StgValue_38 (br ) [ 000000000000] temp (read ) [ 000000001010] empty (speclooptripcount) [ 000000000000] StgValue_41 (specloopname ) [ 000000000000] tmp_3_i_i (specregionbegin ) [ 000000000000] StgValue_43 (specpipeline ) [ 000000000000] StgValue_44 (write ) [ 000000000000] empty_10 (specregionend ) [ 000000000000] StgValue_46 (br ) [ 000000011110] StgValue_47 (ret ) [ 000000000000] ---------------- Datapath Model END ------------------ * FSMD analyzer results: - Output states: Port: in_stream_V | {10 } Port: in_array | {} Port: out_array_offset_out | {7 } - Input state : Port: read_pixel13 : in_array | {1 2 3 4 5 6 7 9 } Port: read_pixel13 : in_array_offset | {1 } Port: read_pixel13 : out_array_offset | {7 } - Chain level: State 1 sext_i_i : 1 in_array_addr : 2 in_array_addr_i_i_rd : 3 State 2 State 3 State 4 State 5 State 6 State 7 State 8 exitcond_i_i : 1 i : 1 StgValue_38 : 2 State 9 State 10 empty_10 : 1 State 11 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ * Functional unit list: |----------|----------------------------------|---------|---------| | Operation| Functional Unit | FF | LUT | |----------|----------------------------------|---------|---------| | add | i_fu_169 | 0 | 16 | |----------|----------------------------------|---------|---------| | icmp | exitcond_i_i_fu_163 | 0 | 13 | |----------|----------------------------------|---------|---------| | | in_array_offset_read_read_fu_92 | 0 | 0 | | read | out_array_offset_rea_read_fu_105 | 0 | 0 | | | temp_read_fu_119 | 0 | 0 | |----------|----------------------------------|---------|---------| | readreq | grp_readreq_fu_98 | 0 | 0 | |----------|----------------------------------|---------|---------| | write | StgValue_28_write_fu_111 | 0 | 0 | | | StgValue_44_write_fu_124 | 0 | 0 | |----------|----------------------------------|---------|---------| |partselect| in_array_offset1_i_i_fu_142 | 0 | 0 | |----------|----------------------------------|---------|---------| | zext | sext_i_i_fu_152 | 0 | 0 | |----------|----------------------------------|---------|---------| | Total | | 0 | 29 | |----------|----------------------------------|---------|---------| Memories: N/A * Register list: +---------------------+--------+ | | FF | +---------------------+--------+ | exitcond_i_i_reg_181| 1 | | i_i_i_reg_131 | 9 | | i_reg_185 | 9 | |in_array_addr_reg_175| 32 | | temp_reg_190 | 32 | +---------------------+--------+ | Total | 83 | +---------------------+--------+ * Multiplexer (MUX) list: |-------------------|------|------|------|--------||---------||---------| | Comp | Pin | Size | BW | S x BW || Delay || LUT | |-------------------|------|------|------|--------||---------||---------| | grp_readreq_fu_98 | p1 | 2 | 32 | 64 || 9 | |-------------------|------|------|------|--------||---------||---------| | Total | | | | 64 || 1.769 || 9 | |-------------------|------|------|------|--------||---------||---------| * Summary: +-----------+--------+--------+--------+ | | Delay | FF | LUT | +-----------+--------+--------+--------+ | Function | - | 0 | 29 | | Memory | - | - | - | |Multiplexer| 1 | - | 9 | | Register | - | 83 | - | +-----------+--------+--------+--------+ | Total | 1 | 83 | 38 | +-----------+--------+--------+--------+