================================================================
== Vivado HLS Report for 'read_pixel13'
================================================================
* Date:           Wed May 30 11:44:02 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       axi_port_only
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      8.75|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |  409|  409|  409|  409|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +-------------+-----+-----+----------+-----------+-----------+------+----------+
        |             |  Latency  | Iteration|  Initiation Interval  | Trip |          |
        |  Loop Name  | min | max |  Latency |  achieved |   target  | Count| Pipelined|
        +-------------+-----+-----+----------+-----------+-----------+------+----------+
        |- read_loop  |  401|  401|         3|          1|          1|   400|    yes   |
        +-------------+-----+-----+----------+-----------+-----------+------+----------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 0
ResetActiveHigh: 1
IsCombinational: 2
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 1, depth = 3


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 11
* Pipeline : 1
  Pipeline-0 : II = 1, D = 3, States = { 8 9 10 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	4  / true
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	11  / (exitcond_i_i)
	9  / (!exitcond_i_i)
9 --> 
	10  / true
10 --> 
	8  / true
11 --> 

* FSM state operations: 

 <State 1> : 8.75ns
ST_1 : Operation 12 [1/1] (0.00ns)   --->   "%in_array_offset_read = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %in_array_offset)"
ST_1 : Operation 13 [1/1] (0.00ns)   --->   "%in_array_offset1_i_i = call i30 @_ssdm_op_PartSelect.i30.i32.i32.i32(i32 %in_array_offset_read, i32 2, i32 31)"
ST_1 : Operation 14 [1/1] (0.00ns)   --->   "%sext_i_i = zext i30 %in_array_offset1_i_i to i64"
ST_1 : Operation 15 [1/1] (0.00ns)   --->   "%in_array_addr = getelementptr float* %in_array, i64 %sext_i_i"
ST_1 : Operation 16 [7/7] (8.75ns)   --->   "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 2> : 8.75ns
ST_2 : Operation 17 [6/7] (8.75ns)   --->   "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 3> : 8.75ns
ST_3 : Operation 18 [5/7] (8.75ns)   --->   "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 4> : 8.75ns
ST_4 : Operation 19 [4/7] (8.75ns)   --->   "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 5> : 8.75ns
ST_5 : Operation 20 [3/7] (8.75ns)   --->   "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 6> : 8.75ns
ST_6 : Operation 21 [2/7] (8.75ns)   --->   "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 7> : 8.75ns
ST_7 : Operation 22 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)"
ST_7 : Operation 23 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)"
ST_7 : Operation 24 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_7 : Operation 25 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_7 : Operation 26 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(i32* %out_array_offset_out, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str15, i32 0, i32 0, [1 x i8]* @p_str16, [1 x i8]* @p_str17, [1 x i8]* @p_str18, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str19, [1 x i8]* @p_str20)"
ST_7 : Operation 27 [1/1] (0.00ns)   --->   "%out_array_offset_rea = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %out_array_offset)"
ST_7 : Operation 28 [1/1] (3.63ns)   --->   "call void @_ssdm_op_Write.ap_fifo.i32P(i32* %out_array_offset_out, i32 %out_array_offset_rea)"   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_7 : Operation 29 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)"
ST_7 : Operation 30 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_7 : Operation 31 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)"
ST_7 : Operation 32 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)"
ST_7 : Operation 33 [1/7] (8.75ns)   --->   "%in_array_addr_i_i_rd = call i1 @_ssdm_op_ReadReq.m_axi.floatP(float* %in_array_addr, i32 400)" [edge_detection/edge_detection.cpp:15]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>
ST_7 : Operation 34 [1/1] (1.76ns)   --->   "br label %0" [edge_detection/edge_detection.cpp:14]

 <State 8> : 1.94ns
ST_8 : Operation 35 [1/1] (0.00ns)   --->   "%i_i_i = phi i9 [ 0, %entry ], [ %i, %1 ]"
ST_8 : Operation 36 [1/1] (1.66ns)   --->   "%exitcond_i_i = icmp eq i9 %i_i_i, -112" [edge_detection/edge_detection.cpp:14]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.66> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_8 : Operation 37 [1/1] (1.93ns)   --->   "%i = add i9 %i_i_i, 1" [edge_detection/edge_detection.cpp:14]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.93> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_8 : Operation 38 [1/1] (0.00ns)   --->   "br i1 %exitcond_i_i, label %.exit, label %1" [edge_detection/edge_detection.cpp:14]

 <State 9> : 8.75ns
ST_9 : Operation 39 [1/1] (8.75ns)   --->   "%temp = call float @_ssdm_op_Read.m_axi.floatP(float* %in_array_addr)" [edge_detection/edge_detection.cpp:15]   --->   Core 9 'm_axi' <Latency = 6> <II = 1> <Delay = 1.00> <Adapter> <Opcode : 'read' 'write' 'readreq' 'writereq' 'writeresp'>

 <State 10> : 3.63ns
ST_10 : Operation 40 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 400, i64 400, i64 400)"
ST_10 : Operation 41 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecLoopName([10 x i8]* @p_str) nounwind" [edge_detection/edge_detection.cpp:14]
ST_10 : Operation 42 [1/1] (0.00ns)   --->   "%tmp_3_i_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([10 x i8]* @p_str)" [edge_detection/edge_detection.cpp:14]
ST_10 : Operation 43 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:15]
ST_10 : Operation 44 [1/1] (3.63ns)   --->   "call void @_ssdm_op_Write.ap_fifo.volatile.floatP(float* %in_stream_V, float %temp)" [edge_detection/edge_detection.cpp:16]   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_10 : Operation 45 [1/1] (0.00ns)   --->   "%empty_10 = call i32 (...)* @_ssdm_op_SpecRegionEnd([10 x i8]* @p_str, i32 %tmp_3_i_i)" [edge_detection/edge_detection.cpp:17]
ST_10 : Operation 46 [1/1] (0.00ns)   --->   "br label %0" [edge_detection/edge_detection.cpp:14]

 <State 11> : 0.00ns
ST_11 : Operation 47 [1/1] (0.00ns)   --->   "ret void"


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 0
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ in_stream_V]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ in_array]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0
Port [ in_array_offset]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ out_array_offset]:  wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0
Port [ out_array_offset_out]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
in_array_offset_read (read             ) [ 000000000000]
in_array_offset1_i_i (partselect       ) [ 000000000000]
sext_i_i             (zext             ) [ 000000000000]
in_array_addr        (getelementptr    ) [ 001111111110]
StgValue_22          (specinterface    ) [ 000000000000]
StgValue_23          (specinterface    ) [ 000000000000]
StgValue_24          (specinterface    ) [ 000000000000]
StgValue_25          (specinterface    ) [ 000000000000]
StgValue_26          (specinterface    ) [ 000000000000]
out_array_offset_rea (read             ) [ 000000000000]
StgValue_28          (write            ) [ 000000000000]
StgValue_29          (specinterface    ) [ 000000000000]
StgValue_30          (specinterface    ) [ 000000000000]
StgValue_31          (specinterface    ) [ 000000000000]
StgValue_32          (specinterface    ) [ 000000000000]
in_array_addr_i_i_rd (readreq          ) [ 000000000000]
StgValue_34          (br               ) [ 000000011110]
i_i_i                (phi              ) [ 000000001000]
exitcond_i_i         (icmp             ) [ 000000001110]
i                    (add              ) [ 000000011110]
StgValue_38          (br               ) [ 000000000000]
temp                 (read             ) [ 000000001010]
empty                (speclooptripcount) [ 000000000000]
StgValue_41          (specloopname     ) [ 000000000000]
tmp_3_i_i            (specregionbegin  ) [ 000000000000]
StgValue_43          (specpipeline     ) [ 000000000000]
StgValue_44          (write            ) [ 000000000000]
empty_10             (specregionend    ) [ 000000000000]
StgValue_46          (br               ) [ 000000011110]
StgValue_47          (ret              ) [ 000000000000]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="in_stream_V">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="in_stream_V"/></StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="in_array">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="in_array"/></StgValue>
</bind>
</comp>

<comp id="4" class="1000" name="in_array_offset">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="in_array_offset"/></StgValue>
</bind>
</comp>

<comp id="6" class="1000" name="out_array_offset">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_array_offset"/></StgValue>
</bind>
</comp>

<comp id="8" class="1000" name="out_array_offset_out">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_array_offset_out"/></StgValue>
</bind>
</comp>

<comp id="10" class="1001" name="const_10">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.ap_auto.i32"/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_PartSelect.i30.i32.i32.i32"/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_ReadReq.m_axi.floatP"/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="ap_fifo_str"/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str37"/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str38"/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str39"/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str40"/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str41"/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str42"/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str7"/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str1"/></StgValue>
</bind>
</comp>

<comp id="46" class="1001" name="const_46">
<pin_list>
<pin id="47" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str8"/></StgValue>
</bind>
</comp>

<comp id="48" class="1001" name="const_48">
<pin_list>
<pin id="49" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str9"/></StgValue>
</bind>
</comp>

<comp id="50" class="1001" name="const_50">
<pin_list>
<pin id="51" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str15"/></StgValue>
</bind>
</comp>

<comp id="52" class="1001" name="const_52">
<pin_list>
<pin id="53" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str16"/></StgValue>
</bind>
</comp>

<comp id="54" class="1001" name="const_54">
<pin_list>
<pin id="55" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str17"/></StgValue>
</bind>
</comp>

<comp id="56" class="1001" name="const_56">
<pin_list>
<pin id="57" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str18"/></StgValue>
</bind>
</comp>

<comp id="58" class="1001" name="const_58">
<pin_list>
<pin id="59" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str19"/></StgValue>
</bind>
</comp>

<comp id="60" class="1001" name="const_60">
<pin_list>
<pin id="61" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str20"/></StgValue>
</bind>
</comp>

<comp id="62" class="1001" name="const_62">
<pin_list>
<pin id="63" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.ap_fifo.i32P"/></StgValue>
</bind>
</comp>

<comp id="64" class="1001" name="const_64">
<pin_list>
<pin id="65" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="66" class="1001" name="const_66">
<pin_list>
<pin id="67" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="68" class="1001" name="const_68">
<pin_list>
<pin id="69" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="70" class="1001" name="const_70">
<pin_list>
<pin id="71" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.m_axi.floatP"/></StgValue>
</bind>
</comp>

<comp id="72" class="1001" name="const_72">
<pin_list>
<pin id="73" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopTripCount"/></StgValue>
</bind>
</comp>

<comp id="74" class="1001" name="const_74">
<pin_list>
<pin id="75" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="76" class="1001" name="const_76">
<pin_list>
<pin id="77" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopName"/></StgValue>
</bind>
</comp>

<comp id="78" class="1001" name="const_78">
<pin_list>
<pin id="79" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str"/></StgValue>
</bind>
</comp>

<comp id="80" class="1001" name="const_80">
<pin_list>
<pin id="81" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionBegin"/></StgValue>
</bind>
</comp>

<comp id="82" class="1001" name="const_82">
<pin_list>
<pin id="83" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecPipeline"/></StgValue>
</bind>
</comp>

<comp id="84" class="1001" name="const_84">
<pin_list>
<pin id="85" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="86" class="1001" name="const_86">
<pin_list>
<pin id="87" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="88" class="1001" name="const_88">
<pin_list>
<pin id="89" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.ap_fifo.volatile.floatP"/></StgValue>
</bind>
</comp>

<comp id="90" class="1001" name="const_90">
<pin_list>
<pin id="91" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionEnd"/></StgValue>
</bind>
</comp>

<comp id="92" class="1004" name="in_array_offset_read_read_fu_92">
<pin_list>
<pin id="93" dir="0" index="0" bw="32" slack="0"/>
<pin id="94" dir="0" index="1" bw="32" slack="0"/>
<pin id="95" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="in_array_offset_read/1 "/>
</bind>
</comp>

<comp id="98" class="1004" name="grp_readreq_fu_98">
<pin_list>
<pin id="99" dir="0" index="0" bw="1" slack="0"/>
<pin id="100" dir="0" index="1" bw="32" slack="0"/>
<pin id="101" dir="0" index="2" bw="10" slack="0"/>
<pin id="102" dir="1" index="3" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opcode="readreq(1154) " fcode="readreq"/>
<opset="in_array_addr_i_i_rd/1 "/>
</bind>
</comp>

<comp id="105" class="1004" name="out_array_offset_rea_read_fu_105">
<pin_list>
<pin id="106" dir="0" index="0" bw="32" slack="0"/>
<pin id="107" dir="0" index="1" bw="32" slack="0"/>
<pin id="108" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="out_array_offset_rea/7 "/>
</bind>
</comp>

<comp id="111" class="1004" name="StgValue_28_write_fu_111">
<pin_list>
<pin id="112" dir="0" index="0" bw="0" slack="0"/>
<pin id="113" dir="0" index="1" bw="32" slack="0"/>
<pin id="114" dir="0" index="2" bw="32" slack="0"/>
<pin id="115" dir="1" index="3" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_28/7 "/>
</bind>
</comp>

<comp id="119" class="1004" name="temp_read_fu_119">
<pin_list>
<pin id="120" dir="0" index="0" bw="32" slack="0"/>
<pin id="121" dir="0" index="1" bw="32" slack="8"/>
<pin id="122" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="temp/9 "/>
</bind>
</comp>

<comp id="124" class="1004" name="StgValue_44_write_fu_124">
<pin_list>
<pin id="125" dir="0" index="0" bw="0" slack="0"/>
<pin id="126" dir="0" index="1" bw="32" slack="0"/>
<pin id="127" dir="0" index="2" bw="32" slack="1"/>
<pin id="128" dir="1" index="3" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_44/10 "/>
</bind>
</comp>

<comp id="131" class="1005" name="i_i_i_reg_131">
<pin_list>
<pin id="132" dir="0" index="0" bw="9" slack="1"/>
<pin id="133" dir="1" index="1" bw="9" slack="1"/>
</pin_list>
<bind>
<opset="i_i_i (phireg) "/>
</bind>
</comp>

<comp id="135" class="1004" name="i_i_i_phi_fu_135">
<pin_list>
<pin id="136" dir="0" index="0" bw="1" slack="1"/>
<pin id="137" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="138" dir="0" index="2" bw="9" slack="0"/>
<pin id="139" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="140" dir="1" index="4" bw="9" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="i_i_i/8 "/>
</bind>
</comp>

<comp id="142" class="1004" name="in_array_offset1_i_i_fu_142">
<pin_list>
<pin id="143" dir="0" index="0" bw="30" slack="0"/>
<pin id="144" dir="0" index="1" bw="32" slack="0"/>
<pin id="145" dir="0" index="2" bw="3" slack="0"/>
<pin id="146" dir="0" index="3" bw="6" slack="0"/>
<pin id="147" dir="1" index="4" bw="30" slack="0"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="in_array_offset1_i_i/1 "/>
</bind>
</comp>

<comp id="152" class="1004" name="sext_i_i_fu_152">
<pin_list>
<pin id="153" dir="0" index="0" bw="30" slack="0"/>
<pin id="154" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="sext_i_i/1 "/>
</bind>
</comp>

<comp id="156" class="1004" name="in_array_addr_fu_156">
<pin_list>
<pin id="157" dir="0" index="0" bw="32" slack="0"/>
<pin id="158" dir="0" index="1" bw="30" slack="0"/>
<pin id="159" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="in_array_addr/1 "/>
</bind>
</comp>

<comp id="163" class="1004" name="exitcond_i_i_fu_163">
<pin_list>
<pin id="164" dir="0" index="0" bw="9" slack="0"/>
<pin id="165" dir="0" index="1" bw="8" slack="0"/>
<pin id="166" dir="1" index="2" bw="1" slack="1"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond_i_i/8 "/>
</bind>
</comp>

<comp id="169" class="1004" name="i_fu_169">
<pin_list>
<pin id="170" dir="0" index="0" bw="9" slack="0"/>
<pin id="171" dir="0" index="1" bw="1" slack="0"/>
<pin id="172" dir="1" index="2" bw="9" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="i/8 "/>
</bind>
</comp>

<comp id="175" class="1005" name="in_array_addr_reg_175">
<pin_list>
<pin id="176" dir="0" index="0" bw="32" slack="1"/>
<pin id="177" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="in_array_addr "/>
</bind>
</comp>

<comp id="181" class="1005" name="exitcond_i_i_reg_181">
<pin_list>
<pin id="182" dir="0" index="0" bw="1" slack="1"/>
<pin id="183" dir="1" index="1" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opset="exitcond_i_i "/>
</bind>
</comp>

<comp id="185" class="1005" name="i_reg_185">
<pin_list>
<pin id="186" dir="0" index="0" bw="9" slack="0"/>
<pin id="187" dir="1" index="1" bw="9" slack="0"/>
</pin_list>
<bind>
<opset="i "/>
</bind>
</comp>

<comp id="190" class="1005" name="temp_reg_190">
<pin_list>
<pin id="191" dir="0" index="0" bw="32" slack="1"/>
<pin id="192" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="temp "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="96"><net_src comp="10" pin="0"/><net_sink comp="92" pin=0"/></net>

<net id="97"><net_src comp="4" pin="0"/><net_sink comp="92" pin=1"/></net>

<net id="103"><net_src comp="18" pin="0"/><net_sink comp="98" pin=0"/></net>

<net id="104"><net_src comp="20" pin="0"/><net_sink comp="98" pin=2"/></net>

<net id="109"><net_src comp="10" pin="0"/><net_sink comp="105" pin=0"/></net>

<net id="110"><net_src comp="6" pin="0"/><net_sink comp="105" pin=1"/></net>

<net id="116"><net_src comp="62" pin="0"/><net_sink comp="111" pin=0"/></net>

<net id="117"><net_src comp="8" pin="0"/><net_sink comp="111" pin=1"/></net>

<net id="118"><net_src comp="105" pin="2"/><net_sink comp="111" pin=2"/></net>

<net id="123"><net_src comp="70" pin="0"/><net_sink comp="119" pin=0"/></net>

<net id="129"><net_src comp="88" pin="0"/><net_sink comp="124" pin=0"/></net>

<net id="130"><net_src comp="0" pin="0"/><net_sink comp="124" pin=1"/></net>

<net id="134"><net_src comp="64" pin="0"/><net_sink comp="131" pin=0"/></net>

<net id="141"><net_src comp="131" pin="1"/><net_sink comp="135" pin=0"/></net>

<net id="148"><net_src comp="12" pin="0"/><net_sink comp="142" pin=0"/></net>

<net id="149"><net_src comp="92" pin="2"/><net_sink comp="142" pin=1"/></net>

<net id="150"><net_src comp="14" pin="0"/><net_sink comp="142" pin=2"/></net>

<net id="151"><net_src comp="16" pin="0"/><net_sink comp="142" pin=3"/></net>

<net id="155"><net_src comp="142" pin="4"/><net_sink comp="152" pin=0"/></net>

<net id="160"><net_src comp="2" pin="0"/><net_sink comp="156" pin=0"/></net>

<net id="161"><net_src comp="152" pin="1"/><net_sink comp="156" pin=1"/></net>

<net id="162"><net_src comp="156" pin="2"/><net_sink comp="98" pin=1"/></net>

<net id="167"><net_src comp="135" pin="4"/><net_sink comp="163" pin=0"/></net>

<net id="168"><net_src comp="66" pin="0"/><net_sink comp="163" pin=1"/></net>

<net id="173"><net_src comp="135" pin="4"/><net_sink comp="169" pin=0"/></net>

<net id="174"><net_src comp="68" pin="0"/><net_sink comp="169" pin=1"/></net>

<net id="178"><net_src comp="156" pin="2"/><net_sink comp="175" pin=0"/></net>

<net id="179"><net_src comp="175" pin="1"/><net_sink comp="98" pin=1"/></net>

<net id="180"><net_src comp="175" pin="1"/><net_sink comp="119" pin=1"/></net>

<net id="184"><net_src comp="163" pin="2"/><net_sink comp="181" pin=0"/></net>

<net id="188"><net_src comp="169" pin="2"/><net_sink comp="185" pin=0"/></net>

<net id="189"><net_src comp="185" pin="1"/><net_sink comp="135" pin=2"/></net>

<net id="193"><net_src comp="119" pin="2"/><net_sink comp="190" pin=0"/></net>

<net id="194"><net_src comp="190" pin="1"/><net_sink comp="124" pin=2"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: in_stream_V | {10 }
	Port: out_array_offset_out | {7 }
 - Input state : 
	Port: read_pixel13 : in_array | {1 2 3 4 5 6 7 9 }
	Port: read_pixel13 : in_array_offset | {1 }
	Port: read_pixel13 : out_array_offset | {7 }
  - Chain level:
	State 1
		sext_i_i : 1
		in_array_addr : 2
		in_array_addr_i_i_rd : 3
	State 2
	State 3
	State 4
	State 5
	State 6
	State 7
	State 8
		exitcond_i_i : 1
		i : 1
		StgValue_38 : 2
	State 9
	State 10
		empty_10 : 1
	State 11


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|----------------------------------|---------|---------|
| Operation|          Functional Unit         |    FF   |   LUT   |
|----------|----------------------------------|---------|---------|
|    add   |             i_fu_169             |    0    |    16   |
|----------|----------------------------------|---------|---------|
|   icmp   |        exitcond_i_i_fu_163       |    0    |    13   |
|----------|----------------------------------|---------|---------|
|          |  in_array_offset_read_read_fu_92 |    0    |    0    |
|   read   | out_array_offset_rea_read_fu_105 |    0    |    0    |
|          |         temp_read_fu_119         |    0    |    0    |
|----------|----------------------------------|---------|---------|
|  readreq |         grp_readreq_fu_98        |    0    |    0    |
|----------|----------------------------------|---------|---------|
|   write  |     StgValue_28_write_fu_111     |    0    |    0    |
|          |     StgValue_44_write_fu_124     |    0    |    0    |
|----------|----------------------------------|---------|---------|
|partselect|    in_array_offset1_i_i_fu_142   |    0    |    0    |
|----------|----------------------------------|---------|---------|
|   zext   |          sext_i_i_fu_152         |    0    |    0    |
|----------|----------------------------------|---------|---------|
|   Total  |                                  |    0    |    29   |
|----------|----------------------------------|---------|---------|

Memories:
N/A

* Register list:
+---------------------+--------+
|                     |   FF   |
+---------------------+--------+
| exitcond_i_i_reg_181|    1   |
|    i_i_i_reg_131    |    9   |
|      i_reg_185      |    9   |
|in_array_addr_reg_175|   32   |
|     temp_reg_190    |   32   |
+---------------------+--------+
|        Total        |   83   |
+---------------------+--------+

* Multiplexer (MUX) list: 
|-------------------|------|------|------|--------||---------||---------|
|        Comp       |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|-------------------|------|------|------|--------||---------||---------|
| grp_readreq_fu_98 |  p1  |   2  |  32  |   64   ||    9    |
|-------------------|------|------|------|--------||---------||---------|
|       Total       |      |      |      |   64   ||  1.769  ||    9    |
|-------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+
|           |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+
|  Function |    -   |    0   |   29   |
|   Memory  |    -   |    -   |    -   |
|Multiplexer|    1   |    -   |    9   |
|  Register |    -   |   83   |    -   |
+-----------+--------+--------+--------+
|   Total   |    1   |   83   |   38   |
+-----------+--------+--------+--------+