================================================================
== Vivado HLS Report for 'move_data'
================================================================
* Date:           Tue May 29 19:06:42 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       axi_port_only
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      4.64|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+----------+
    |  Latency  |  Interval | Pipeline |
    | min | max | min | max |   Type   |
    +-----+-----+-----+-----+----------+
    |    7|    7|    8|    8| function |
    +-----+-----+-----+-----+----------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        N/A

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 0
ResetActiveHigh: 1
IsCombinational: 0
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 2
HasVarLatency: 0
IsPipeline: 1
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 8, depth = 8


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 8
* Pipeline : 1
  Pipeline-0 : II = 8, D = 8, States = { 1 2 3 4 5 6 7 8 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	4  / true
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 

* FSM state operations: 

 <State 1> : 2.32ns
ST_1 : Operation 9 [1/1] (0.00ns)   --->   "%crop_addr = getelementptr [9 x float]* %crop, i64 0, i64 1" [edge_detection/edge_detection.cpp:28]
ST_1 : Operation 10 [1/1] (0.00ns)   --->   "%crop_addr_1 = getelementptr [9 x float]* %crop, i64 0, i64 2" [edge_detection/edge_detection.cpp:28]
ST_1 : Operation 11 [2/2] (2.32ns)   --->   "%crop_load = load float* %crop_addr, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_1 : Operation 12 [2/2] (2.32ns)   --->   "%crop_load_1 = load float* %crop_addr_1, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>

 <State 2> : 2.32ns
ST_2 : Operation 13 [1/1] (0.00ns)   --->   "%crop_addr_2 = getelementptr [9 x float]* %crop, i64 0, i64 4" [edge_detection/edge_detection.cpp:28]
ST_2 : Operation 14 [1/1] (0.00ns)   --->   "%crop_addr_3 = getelementptr [9 x float]* %crop, i64 0, i64 5" [edge_detection/edge_detection.cpp:28]
ST_2 : Operation 15 [1/2] (2.32ns)   --->   "%crop_load = load float* %crop_addr, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_2 : Operation 16 [1/2] (2.32ns)   --->   "%crop_load_1 = load float* %crop_addr_1, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_2 : Operation 17 [2/2] (2.32ns)   --->   "%crop_load_2 = load float* %crop_addr_2, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_2 : Operation 18 [2/2] (2.32ns)   --->   "%crop_load_3 = load float* %crop_addr_3, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>

 <State 3> : 2.32ns
ST_3 : Operation 19 [1/1] (0.00ns)   --->   "%crop_addr_4 = getelementptr [9 x float]* %crop, i64 0, i64 7" [edge_detection/edge_detection.cpp:28]
ST_3 : Operation 20 [1/1] (0.00ns)   --->   "%crop_addr_5 = getelementptr [9 x float]* %crop, i64 0, i64 8" [edge_detection/edge_detection.cpp:28]
ST_3 : Operation 21 [1/2] (2.32ns)   --->   "%crop_load_2 = load float* %crop_addr_2, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_3 : Operation 22 [1/2] (2.32ns)   --->   "%crop_load_3 = load float* %crop_addr_3, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_3 : Operation 23 [2/2] (2.32ns)   --->   "%crop_load_4 = load float* %crop_addr_4, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_3 : Operation 24 [2/2] (2.32ns)   --->   "%crop_load_5 = load float* %crop_addr_5, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>

 <State 4> : 2.32ns
ST_4 : Operation 25 [1/1] (0.00ns)   --->   "%crop_addr_6 = getelementptr [9 x float]* %crop, i64 0, i64 0" [edge_detection/edge_detection.cpp:31]
ST_4 : Operation 26 [1/2] (2.32ns)   --->   "%crop_load_4 = load float* %crop_addr_4, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_4 : Operation 27 [1/2] (2.32ns)   --->   "%crop_load_5 = load float* %crop_addr_5, align 4" [edge_detection/edge_detection.cpp:28]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_4 : Operation 28 [1/1] (2.32ns)   --->   "store float %crop_load, float* %crop_addr_6, align 4" [edge_detection/edge_detection.cpp:31]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_4 : Operation 29 [1/1] (2.32ns)   --->   "store float %crop_load_1, float* %crop_addr, align 4" [edge_detection/edge_detection.cpp:31]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>

 <State 5> : 2.32ns
ST_5 : Operation 30 [1/1] (0.00ns)   --->   "%crop_addr_7 = getelementptr [9 x float]* %crop, i64 0, i64 3" [edge_detection/edge_detection.cpp:31]
ST_5 : Operation 31 [1/1] (2.32ns)   --->   "store float %crop_load_2, float* %crop_addr_7, align 4" [edge_detection/edge_detection.cpp:31]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_5 : Operation 32 [1/1] (2.32ns)   --->   "store float %crop_load_3, float* %crop_addr_2, align 4" [edge_detection/edge_detection.cpp:31]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>

 <State 6> : 2.32ns
ST_6 : Operation 33 [1/1] (0.00ns)   --->   "%pos_y_read = call i6 @_ssdm_op_Read.ap_auto.i6(i6 %pos_y)"
ST_6 : Operation 34 [1/1] (0.00ns)   --->   "%crop_addr_8 = getelementptr [9 x float]* %crop, i64 0, i64 6" [edge_detection/edge_detection.cpp:31]
ST_6 : Operation 35 [1/1] (2.32ns)   --->   "store float %crop_load_4, float* %crop_addr_8, align 4" [edge_detection/edge_detection.cpp:31]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_6 : Operation 36 [1/1] (2.32ns)   --->   "store float %crop_load_5, float* %crop_addr_4, align 4" [edge_detection/edge_detection.cpp:31]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_6 : Operation 37 [1/1] (0.00ns)   --->   "%tmp_6 = zext i6 %pos_y_read to i64" [edge_detection/edge_detection.cpp:33]
ST_6 : Operation 38 [1/1] (0.00ns)   --->   "%temp_array_0_addr = getelementptr [20 x float]* %temp_array_0, i64 0, i64 %tmp_6" [edge_detection/edge_detection.cpp:33]
ST_6 : Operation 39 [2/2] (2.32ns)   --->   "%temp_array_0_load = load float* %temp_array_0_addr, align 4" [edge_detection/edge_detection.cpp:33]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_6 : Operation 40 [1/1] (0.00ns)   --->   "%temp_array_1_addr = getelementptr [20 x float]* %temp_array_1, i64 0, i64 %tmp_6" [edge_detection/edge_detection.cpp:33]
ST_6 : Operation 41 [2/2] (2.32ns)   --->   "%temp_array_1_load = load float* %temp_array_1_addr, align 4" [edge_detection/edge_detection.cpp:33]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>

 <State 7> : 4.64ns
ST_7 : Operation 42 [1/2] (2.32ns)   --->   "%temp_array_0_load = load float* %temp_array_0_addr, align 4" [edge_detection/edge_detection.cpp:33]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_7 : Operation 43 [1/1] (2.32ns)   --->   "store float %temp_array_0_load, float* %crop_addr_1, align 4" [edge_detection/edge_detection.cpp:33]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_7 : Operation 44 [1/2] (2.32ns)   --->   "%temp_array_1_load = load float* %temp_array_1_addr, align 4" [edge_detection/edge_detection.cpp:33]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_7 : Operation 45 [1/1] (2.32ns)   --->   "store float %temp_array_1_load, float* %crop_addr_3, align 4" [edge_detection/edge_detection.cpp:33]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_7 : Operation 46 [1/1] (2.32ns)   --->   "store float %temp_array_1_load, float* %temp_array_0_addr, align 4" [edge_detection/edge_detection.cpp:37]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>

 <State 8> : 2.32ns
ST_8 : Operation 47 [1/1] (0.00ns)   --->   "%new_data_read = call float @_ssdm_op_Read.ap_auto.float(float %new_data)"
ST_8 : Operation 48 [1/1] (2.32ns)   --->   "store float %new_data_read, float* %crop_addr_5, align 4" [edge_detection/edge_detection.cpp:34]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_8 : Operation 49 [1/1] (2.32ns)   --->   "store float %new_data_read, float* %temp_array_1_addr, align 4" [edge_detection/edge_detection.cpp:38]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_8 : Operation 50 [1/1] (0.00ns)   --->   "ret void" [edge_detection/edge_detection.cpp:39]


============================================================
+ Verbose Summary: Timing violations
============================================================
Target clock period: 10ns, clock uncertainty: 1.25ns.

 <State 1>: 2.32ns
The critical path consists of the following:
	'getelementptr' operation ('crop_addr', edge_detection/edge_detection.cpp:28) [8]  (0 ns)
	'load' operation ('crop_load', edge_detection/edge_detection.cpp:28) on array 'crop' [17]  (2.32 ns)

 <State 2>: 2.32ns
The critical path consists of the following:
	'getelementptr' operation ('crop_addr_2', edge_detection/edge_detection.cpp:28) [10]  (0 ns)
	'load' operation ('crop_load_2', edge_detection/edge_detection.cpp:28) on array 'crop' [19]  (2.32 ns)

 <State 3>: 2.32ns
The critical path consists of the following:
	'getelementptr' operation ('crop_addr_4', edge_detection/edge_detection.cpp:28) [12]  (0 ns)
	'load' operation ('crop_load_4', edge_detection/edge_detection.cpp:28) on array 'crop' [21]  (2.32 ns)

 <State 4>: 2.32ns
The critical path consists of the following:
	'getelementptr' operation ('crop_addr_6', edge_detection/edge_detection.cpp:31) [14]  (0 ns)
	'store' operation (edge_detection/edge_detection.cpp:31) of variable 'crop_load', edge_detection/edge_detection.cpp:28 on array 'crop' [23]  (2.32 ns)

 <State 5>: 2.32ns
The critical path consists of the following:
	'getelementptr' operation ('crop_addr_7', edge_detection/edge_detection.cpp:31) [15]  (0 ns)
	'store' operation (edge_detection/edge_detection.cpp:31) of variable 'crop_load_2', edge_detection/edge_detection.cpp:28 on array 'crop' [25]  (2.32 ns)

 <State 6>: 2.32ns
The critical path consists of the following:
	wire read on port 'pos_y' [6]  (0 ns)
	'getelementptr' operation ('temp_array_0_addr', edge_detection/edge_detection.cpp:33) [30]  (0 ns)
	'load' operation ('temp_array_0_load', edge_detection/edge_detection.cpp:33) on array 'temp_array_0' [31]  (2.32 ns)

 <State 7>: 4.64ns
The critical path consists of the following:
	'load' operation ('temp_array_0_load', edge_detection/edge_detection.cpp:33) on array 'temp_array_0' [31]  (2.32 ns)
	'store' operation (edge_detection/edge_detection.cpp:33) of variable 'temp_array_0_load', edge_detection/edge_detection.cpp:33 on array 'crop' [32]  (2.32 ns)

 <State 8>: 2.32ns
The critical path consists of the following:
	wire read on port 'new_data' [7]  (0 ns)
	'store' operation (edge_detection/edge_detection.cpp:34) of variable 'new_data' on array 'crop' [36]  (2.32 ns)


============================================================
+ Verbose Summary: Binding
============================================================
N/A
* FSMD analyzer results:
  - Output states:
 - Input state : 
  - Chain level:
	State 1
	State 2
	State 3
	State 4
	State 5
	State 6
	State 7
	State 8


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================
N/A