================================================================ == Vivado HLS Report for 'move_data' ================================================================ * Date: Tue May 29 19:06:42 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: axi_port_only * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 4.64| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+----------+ | Latency | Interval | Pipeline | | min | max | min | max | Type | +-----+-----+-----+-----+----------+ | 7| 7| 8| 8| function | +-----+-----+-----+-----+----------+ + Detail: * Instance: N/A * Loop: N/A ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 0 ResetActiveHigh: 1 IsCombinational: 0 IsDatapathOnly: 0 HasWiredReturn: 1 HasMFsm: 2 HasVarLatency: 0 IsPipeline: 1 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 + Individual pipeline summary: * Pipeline-0: initiation interval (II) = 8, depth = 8 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 8 * Pipeline : 1 Pipeline-0 : II = 8, D = 8, States = { 1 2 3 4 5 6 7 8 } * Dataflow Pipeline: 0 * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> 7 / true 7 --> 8 / true 8 --> * FSM state operations: : 2.32ns ST_1 : Operation 9 [1/1] (0.00ns) ---> "%crop_addr = getelementptr [9 x float]* %crop, i64 0, i64 1" [edge_detection/edge_detection.cpp:28] ST_1 : Operation 10 [1/1] (0.00ns) ---> "%crop_addr_1 = getelementptr [9 x float]* %crop, i64 0, i64 2" [edge_detection/edge_detection.cpp:28] ST_1 : Operation 11 [2/2] (2.32ns) ---> "%crop_load = load float* %crop_addr, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_1 : Operation 12 [2/2] (2.32ns) ---> "%crop_load_1 = load float* %crop_addr_1, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' : 2.32ns ST_2 : Operation 13 [1/1] (0.00ns) ---> "%crop_addr_2 = getelementptr [9 x float]* %crop, i64 0, i64 4" [edge_detection/edge_detection.cpp:28] ST_2 : Operation 14 [1/1] (0.00ns) ---> "%crop_addr_3 = getelementptr [9 x float]* %crop, i64 0, i64 5" [edge_detection/edge_detection.cpp:28] ST_2 : Operation 15 [1/2] (2.32ns) ---> "%crop_load = load float* %crop_addr, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_2 : Operation 16 [1/2] (2.32ns) ---> "%crop_load_1 = load float* %crop_addr_1, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_2 : Operation 17 [2/2] (2.32ns) ---> "%crop_load_2 = load float* %crop_addr_2, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_2 : Operation 18 [2/2] (2.32ns) ---> "%crop_load_3 = load float* %crop_addr_3, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' : 2.32ns ST_3 : Operation 19 [1/1] (0.00ns) ---> "%crop_addr_4 = getelementptr [9 x float]* %crop, i64 0, i64 7" [edge_detection/edge_detection.cpp:28] ST_3 : Operation 20 [1/1] (0.00ns) ---> "%crop_addr_5 = getelementptr [9 x float]* %crop, i64 0, i64 8" [edge_detection/edge_detection.cpp:28] ST_3 : Operation 21 [1/2] (2.32ns) ---> "%crop_load_2 = load float* %crop_addr_2, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_3 : Operation 22 [1/2] (2.32ns) ---> "%crop_load_3 = load float* %crop_addr_3, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_3 : Operation 23 [2/2] (2.32ns) ---> "%crop_load_4 = load float* %crop_addr_4, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_3 : Operation 24 [2/2] (2.32ns) ---> "%crop_load_5 = load float* %crop_addr_5, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' : 2.32ns ST_4 : Operation 25 [1/1] (0.00ns) ---> "%crop_addr_6 = getelementptr [9 x float]* %crop, i64 0, i64 0" [edge_detection/edge_detection.cpp:31] ST_4 : Operation 26 [1/2] (2.32ns) ---> "%crop_load_4 = load float* %crop_addr_4, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_4 : Operation 27 [1/2] (2.32ns) ---> "%crop_load_5 = load float* %crop_addr_5, align 4" [edge_detection/edge_detection.cpp:28] ---> Core 37 'RAM' ST_4 : Operation 28 [1/1] (2.32ns) ---> "store float %crop_load, float* %crop_addr_6, align 4" [edge_detection/edge_detection.cpp:31] ---> Core 37 'RAM' ST_4 : Operation 29 [1/1] (2.32ns) ---> "store float %crop_load_1, float* %crop_addr, align 4" [edge_detection/edge_detection.cpp:31] ---> Core 37 'RAM' : 2.32ns ST_5 : Operation 30 [1/1] (0.00ns) ---> "%crop_addr_7 = getelementptr [9 x float]* %crop, i64 0, i64 3" [edge_detection/edge_detection.cpp:31] ST_5 : Operation 31 [1/1] (2.32ns) ---> "store float %crop_load_2, float* %crop_addr_7, align 4" [edge_detection/edge_detection.cpp:31] ---> Core 37 'RAM' ST_5 : Operation 32 [1/1] (2.32ns) ---> "store float %crop_load_3, float* %crop_addr_2, align 4" [edge_detection/edge_detection.cpp:31] ---> Core 37 'RAM' : 2.32ns ST_6 : Operation 33 [1/1] (0.00ns) ---> "%pos_y_read = call i6 @_ssdm_op_Read.ap_auto.i6(i6 %pos_y)" ST_6 : Operation 34 [1/1] (0.00ns) ---> "%crop_addr_8 = getelementptr [9 x float]* %crop, i64 0, i64 6" [edge_detection/edge_detection.cpp:31] ST_6 : Operation 35 [1/1] (2.32ns) ---> "store float %crop_load_4, float* %crop_addr_8, align 4" [edge_detection/edge_detection.cpp:31] ---> Core 37 'RAM' ST_6 : Operation 36 [1/1] (2.32ns) ---> "store float %crop_load_5, float* %crop_addr_4, align 4" [edge_detection/edge_detection.cpp:31] ---> Core 37 'RAM' ST_6 : Operation 37 [1/1] (0.00ns) ---> "%tmp_6 = zext i6 %pos_y_read to i64" [edge_detection/edge_detection.cpp:33] ST_6 : Operation 38 [1/1] (0.00ns) ---> "%temp_array_0_addr = getelementptr [20 x float]* %temp_array_0, i64 0, i64 %tmp_6" [edge_detection/edge_detection.cpp:33] ST_6 : Operation 39 [2/2] (2.32ns) ---> "%temp_array_0_load = load float* %temp_array_0_addr, align 4" [edge_detection/edge_detection.cpp:33] ---> Core 37 'RAM' ST_6 : Operation 40 [1/1] (0.00ns) ---> "%temp_array_1_addr = getelementptr [20 x float]* %temp_array_1, i64 0, i64 %tmp_6" [edge_detection/edge_detection.cpp:33] ST_6 : Operation 41 [2/2] (2.32ns) ---> "%temp_array_1_load = load float* %temp_array_1_addr, align 4" [edge_detection/edge_detection.cpp:33] ---> Core 37 'RAM' : 4.64ns ST_7 : Operation 42 [1/2] (2.32ns) ---> "%temp_array_0_load = load float* %temp_array_0_addr, align 4" [edge_detection/edge_detection.cpp:33] ---> Core 37 'RAM' ST_7 : Operation 43 [1/1] (2.32ns) ---> "store float %temp_array_0_load, float* %crop_addr_1, align 4" [edge_detection/edge_detection.cpp:33] ---> Core 37 'RAM' ST_7 : Operation 44 [1/2] (2.32ns) ---> "%temp_array_1_load = load float* %temp_array_1_addr, align 4" [edge_detection/edge_detection.cpp:33] ---> Core 37 'RAM' ST_7 : Operation 45 [1/1] (2.32ns) ---> "store float %temp_array_1_load, float* %crop_addr_3, align 4" [edge_detection/edge_detection.cpp:33] ---> Core 37 'RAM' ST_7 : Operation 46 [1/1] (2.32ns) ---> "store float %temp_array_1_load, float* %temp_array_0_addr, align 4" [edge_detection/edge_detection.cpp:37] ---> Core 37 'RAM' : 2.32ns ST_8 : Operation 47 [1/1] (0.00ns) ---> "%new_data_read = call float @_ssdm_op_Read.ap_auto.float(float %new_data)" ST_8 : Operation 48 [1/1] (2.32ns) ---> "store float %new_data_read, float* %crop_addr_5, align 4" [edge_detection/edge_detection.cpp:34] ---> Core 37 'RAM' ST_8 : Operation 49 [1/1] (2.32ns) ---> "store float %new_data_read, float* %temp_array_1_addr, align 4" [edge_detection/edge_detection.cpp:38] ---> Core 37 'RAM' ST_8 : Operation 50 [1/1] (0.00ns) ---> "ret void" [edge_detection/edge_detection.cpp:39] ============================================================ + Verbose Summary: Binding ============================================================ STG Binding: ---------------- STG Properties BEGIN ---------------- - Is combinational: 0 - Is one-state seq: 0 - Is datapath-only: 0 - Is pipelined: 1 - Is top level: 0 Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0 Port [ new_data]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ temp_array_0]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=1; pingpong=0; private_global=0; MemPort=[23]; IO mode=ap_memory:ce=0 Port [ temp_array_1]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=1; pingpong=0; private_global=0; MemPort=[23]; IO mode=ap_memory:ce=0 Port [ crop]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=2; type=1; pingpong=0; private_global=0; MemPort=[22]; IO mode=ap_memory:ce=0 Port [ pos_y]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 ---------------- STG Properties END ------------------ ---------------- Datapath Model BEGIN ---------------- crop_addr (getelementptr) [ 001110000] crop_addr_1 (getelementptr) [ 001111110] crop_addr_2 (getelementptr) [ 000111000] crop_addr_3 (getelementptr) [ 000111110] crop_load (load ) [ 000110000] crop_load_1 (load ) [ 000110000] crop_addr_4 (getelementptr) [ 000011100] crop_addr_5 (getelementptr) [ 000011111] crop_load_2 (load ) [ 000011000] crop_load_3 (load ) [ 000011000] crop_addr_6 (getelementptr) [ 000000000] crop_load_4 (load ) [ 000001100] crop_load_5 (load ) [ 000001100] StgValue_28 (store ) [ 000000000] StgValue_29 (store ) [ 000000000] crop_addr_7 (getelementptr) [ 000000000] StgValue_31 (store ) [ 000000000] StgValue_32 (store ) [ 000000000] pos_y_read (read ) [ 000000000] crop_addr_8 (getelementptr) [ 000000000] StgValue_35 (store ) [ 000000000] StgValue_36 (store ) [ 000000000] tmp_6 (zext ) [ 000000000] temp_array_0_addr (getelementptr) [ 000000010] temp_array_1_addr (getelementptr) [ 000000011] temp_array_0_load (load ) [ 000000000] StgValue_43 (store ) [ 000000000] temp_array_1_load (load ) [ 000000000] StgValue_45 (store ) [ 000000000] StgValue_46 (store ) [ 000000000] new_data_read (read ) [ 000000000] StgValue_48 (store ) [ 000000000] StgValue_49 (store ) [ 000000000] StgValue_50 (ret ) [ 000000000] 2 3 2 3 2 2 ---------------- Datapath Model END ------------------ * FSMD analyzer results: - Output states: Port: temp_array_0 | {7 } Port: temp_array_1 | {8 } Port: crop | {4 5 6 7 8 } - Input state : Port: move_data : new_data | {8 } Port: move_data : temp_array_0 | {6 7 } Port: move_data : temp_array_1 | {6 7 } Port: move_data : crop | {1 2 3 4 } Port: move_data : pos_y | {6 } - Chain level: State 1 crop_load : 1 crop_load_1 : 1 State 2 crop_load_2 : 1 crop_load_3 : 1 State 3 crop_load_4 : 1 crop_load_5 : 1 State 4 StgValue_28 : 1 State 5 StgValue_31 : 1 State 6 StgValue_35 : 1 temp_array_0_addr : 1 temp_array_0_load : 2 temp_array_1_addr : 1 temp_array_1_load : 2 State 7 StgValue_43 : 1 StgValue_45 : 1 StgValue_46 : 1 State 8 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ * Functional unit list: |----------|--------------------------| | Operation| Functional Unit | |----------|--------------------------| | read | pos_y_read_read_fu_32 | | | new_data_read_read_fu_38 | |----------|--------------------------| | zext | tmp_6_fu_171 | |----------|--------------------------| | Total | | |----------|--------------------------| Memories: N/A * Register list: +-------------------------+--------+ | | FF | +-------------------------+--------+ | crop_addr_1_reg_183 | 4 | | crop_addr_2_reg_189 | 4 | | crop_addr_3_reg_195 | 4 | | crop_addr_4_reg_200 | 4 | | crop_addr_5_reg_206 | 4 | | crop_addr_reg_177 | 4 | | crop_load_2_reg_212 | 32 | | crop_load_3_reg_217 | 32 | | reg_161 | 32 | | reg_166 | 32 | |temp_array_0_addr_reg_222| 5 | |temp_array_1_addr_reg_227| 5 | +-------------------------+--------+ | Total | 162 | +-------------------------+--------+ * Multiplexer (MUX) list: |-------------------|------|------|------|--------||---------||---------| | Comp | Pin | Size | BW | S x BW || Delay || LUT | |-------------------|------|------|------|--------||---------||---------| | grp_access_fu_60 | p0 | 11 | 4 | 44 || 50 | | grp_access_fu_60 | p1 | 4 | 32 | 128 || 21 | | grp_access_fu_60 | p3 | 9 | 4 | 36 || 44 | | grp_access_fu_60 | p4 | 3 | 32 | 96 || 15 | | grp_access_fu_139 | p0 | 2 | 5 | 10 || 9 | | grp_access_fu_151 | p0 | 2 | 5 | 10 || 9 | |-------------------|------|------|------|--------||---------||---------| | Total | | | | 324 || 11.3148 || 148 | |-------------------|------|------|------|--------||---------||---------| * Summary: +-----------+--------+--------+--------+ | | Delay | FF | LUT | +-----------+--------+--------+--------+ | Function | - | - | - | | Memory | - | - | - | |Multiplexer| 11 | - | 148 | | Register | - | 162 | - | +-----------+--------+--------+--------+ | Total | 11 | 162 | 148 | +-----------+--------+--------+--------+