================================================================
== Vivado HLS Report for 'convolve'
================================================================
* Date:           Wed May 30 11:44:02 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       axi_port_only
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      7.26|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+---------+
    |  Latency  |  Interval | Pipeline|
    | min | max | min | max |   Type  |
    +-----+-----+-----+-----+---------+
    |  451|  451|  451|  451|   none  |
    +-----+-----+-----+-----+---------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        +-----------------------+-----+-----+----------+-----------+-----------+------+----------+
        |                       |  Latency  | Iteration|  Initiation Interval  | Trip |          |
        |       Loop Name       | min | max |  Latency |  achieved |   target  | Count| Pipelined|
        +-----------------------+-----+-----+----------+-----------+-----------+------+----------+
        |- conv_rows_conv_cols  |  449|  449|        51|          1|          1|   400|    yes   |
        +-----------------------+-----+-----+----------+-----------+-----------+------+----------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 0
ResetActiveHigh: 1
IsCombinational: 2
IsDatapathOnly: 0
HasWiredReturn: 1
HasMFsm: 0
HasVarLatency: 1
IsPipeline: 0
IsRtlPipelined: 0
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 1, depth = 51


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 53
* Pipeline : 1
  Pipeline-0 : II = 1, D = 51, States = { 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	53  / (exitcond_flatten)
	4  / (!exitcond_flatten)
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	10  / true
10 --> 
	11  / true
11 --> 
	12  / true
12 --> 
	13  / true
13 --> 
	14  / true
14 --> 
	15  / true
15 --> 
	16  / true
16 --> 
	17  / true
17 --> 
	18  / true
18 --> 
	19  / true
19 --> 
	20  / true
20 --> 
	21  / true
21 --> 
	22  / true
22 --> 
	23  / true
23 --> 
	24  / true
24 --> 
	25  / true
25 --> 
	26  / true
26 --> 
	27  / true
27 --> 
	28  / true
28 --> 
	29  / true
29 --> 
	30  / true
30 --> 
	31  / true
31 --> 
	32  / true
32 --> 
	33  / true
33 --> 
	34  / true
34 --> 
	35  / true
35 --> 
	36  / true
36 --> 
	37  / true
37 --> 
	38  / true
38 --> 
	39  / true
39 --> 
	40  / true
40 --> 
	41  / true
41 --> 
	42  / true
42 --> 
	43  / true
43 --> 
	44  / true
44 --> 
	45  / true
45 --> 
	46  / true
46 --> 
	47  / true
47 --> 
	48  / true
48 --> 
	49  / true
49 --> 
	50  / true
50 --> 
	51  / true
51 --> 
	52  / true
52 --> 
	2  / true
53 --> 

* FSM state operations: 

 <State 1> : 2.32ns
ST_1 : Operation 54 [1/1] (0.00ns)   --->   "%crop_0_0 = alloca float"
ST_1 : Operation 55 [1/1] (0.00ns)   --->   "%crop_0_1 = alloca float"
ST_1 : Operation 56 [1/1] (0.00ns)   --->   "%crop_1_0 = alloca float"
ST_1 : Operation 57 [1/1] (0.00ns)   --->   "%crop_1_1 = alloca float"
ST_1 : Operation 58 [1/1] (0.00ns)   --->   "%crop_2_0 = alloca float"
ST_1 : Operation 59 [1/1] (0.00ns)   --->   "%crop_2_1 = alloca float"
ST_1 : Operation 60 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %out_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str44, i32 0, i32 0, [1 x i8]* @p_str45, [1 x i8]* @p_str46, [1 x i8]* @p_str47, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str48, [1 x i8]* @p_str49)"
ST_1 : Operation 61 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)"
ST_1 : Operation 62 [1/1] (2.32ns)   --->   "%temp_array_0_assign = alloca [20 x float], align 4"   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_1 : Operation 63 [1/1] (2.32ns)   --->   "%temp_array_1_assign = alloca [20 x float], align 4"   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_1 : Operation 64 [1/1] (1.76ns)   --->   "br label %1" [edge_detection/edge_detection.cpp:55]

 <State 2> : 5.41ns
ST_2 : Operation 65 [1/1] (0.00ns)   --->   "%indvar_flatten = phi i9 [ 0, %0 ], [ %indvar_flatten_next, %._crit_edge ]"
ST_2 : Operation 66 [1/1] (0.00ns)   --->   "%i = phi i5 [ 0, %0 ], [ %i_mid2, %._crit_edge ]" [edge_detection/edge_detection.cpp:56]
ST_2 : Operation 67 [1/1] (0.00ns)   --->   "%pos_y_assign = phi i5 [ 0, %0 ], [ %j, %._crit_edge ]"
ST_2 : Operation 68 [1/1] (1.66ns)   --->   "%exitcond_flatten = icmp eq i9 %indvar_flatten, -112"   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 69 [1/1] (1.93ns)   --->   "%indvar_flatten_next = add i9 %indvar_flatten, 1"   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.78> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 70 [1/1] (1.36ns)   --->   "%exitcond = icmp eq i5 %pos_y_assign, -12" [edge_detection/edge_detection.cpp:56]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 71 [1/1] (1.37ns)   --->   "%pos_y_assign_mid2 = select i1 %exitcond, i5 0, i5 %pos_y_assign" [edge_detection/edge_detection.cpp:56]   --->   Core 26 'Sel' <Latency = 0> <II = 1> <Delay = 1.37> <FuncUnit> <Opcode : 'select'> <InPorts = 3> <OutPorts = 1>
ST_2 : Operation 72 [1/1] (1.78ns)   --->   "%i_s = add i5 %i, 1" [edge_detection/edge_detection.cpp:55]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.78> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 73 [1/1] (0.00ns)   --->   "%tmp = call i4 @_ssdm_op_PartSelect.i4.i5.i32.i32(i5 %i_s, i32 1, i32 4)" [edge_detection/edge_detection.cpp:62]
ST_2 : Operation 74 [1/1] (1.30ns)   --->   "%icmp = icmp ne i4 %tmp, 0" [edge_detection/edge_detection.cpp:62]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 75 [1/1] (0.00ns)   --->   "%tmp_1 = call i4 @_ssdm_op_PartSelect.i4.i5.i32.i32(i5 %i, i32 1, i32 4)" [edge_detection/edge_detection.cpp:62]
ST_2 : Operation 76 [1/1] (1.30ns)   --->   "%icmp1 = icmp ne i4 %tmp_1, 0" [edge_detection/edge_detection.cpp:62]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 77 [1/1] (0.00ns) (grouped into LUT with out node or_cond)   --->   "%tmp_mid2 = select i1 %exitcond, i1 %icmp, i1 %icmp1" [edge_detection/edge_detection.cpp:62]   --->   Core 26 'Sel' <Latency = 0> <II = 1> <Delay = 1.37> <FuncUnit> <Opcode : 'select'> <InPorts = 3> <OutPorts = 1>
ST_2 : Operation 78 [1/1] (1.37ns)   --->   "%i_mid2 = select i1 %exitcond, i5 %i_s, i5 %i" [edge_detection/edge_detection.cpp:56]   --->   Core 26 'Sel' <Latency = 0> <II = 1> <Delay = 1.37> <FuncUnit> <Opcode : 'select'> <InPorts = 3> <OutPorts = 1>
ST_2 : Operation 79 [1/1] (0.00ns)   --->   "%tmp_i = zext i5 %pos_y_assign_mid2 to i64" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]
ST_2 : Operation 80 [1/1] (0.00ns)   --->   "%temp_array_0_assign_1 = getelementptr [20 x float]* %temp_array_0_assign, i64 0, i64 %tmp_i" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]
ST_2 : Operation 81 [2/2] (2.32ns)   --->   "%crop_0_2 = load float* %temp_array_0_assign_1, align 4" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_2 : Operation 82 [1/1] (0.00ns)   --->   "%temp_array_1_assign_1 = getelementptr [20 x float]* %temp_array_1_assign, i64 0, i64 %tmp_i" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]
ST_2 : Operation 83 [2/2] (2.32ns)   --->   "%crop_1_2 = load float* %temp_array_1_assign_1, align 4" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_2 : Operation 84 [1/1] (0.00ns)   --->   "%tmp_3 = call i4 @_ssdm_op_PartSelect.i4.i5.i32.i32(i5 %pos_y_assign_mid2, i32 1, i32 4)" [edge_detection/edge_detection.cpp:62]
ST_2 : Operation 85 [1/1] (1.30ns)   --->   "%icmp2 = icmp ne i4 %tmp_3, 0" [edge_detection/edge_detection.cpp:62]   --->   Core 25 'Cmp' <Latency = 0> <II = 1> <Delay = 1.30> <FuncUnit> <Opcode : 'icmp'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 86 [1/1] (1.37ns) (out node of the LUT)   --->   "%or_cond = and i1 %tmp_mid2, %icmp2" [edge_detection/edge_detection.cpp:62]   --->   Core 27 'LogicGate' <Latency = 0> <II = 1> <Delay = 0.93> <FuncUnit> <Opcode : 'and' 'or' 'xor'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 87 [1/1] (0.00ns)   --->   "br i1 %or_cond, label %2, label %._crit_edge" [edge_detection/edge_detection.cpp:62]
ST_2 : Operation 88 [1/1] (1.78ns)   --->   "%j = add i5 %pos_y_assign_mid2, 1" [edge_detection/edge_detection.cpp:56]   --->   Core 14 'AddSub' <Latency = 0> <II = 1> <Delay = 1.78> <FuncUnit> <Opcode : 'add' 'sub'> <InPorts = 2> <OutPorts = 1>

 <State 3> : 5.96ns
ST_3 : Operation 89 [1/1] (0.00ns)   --->   "%crop_0_0_load = load float* %crop_0_0" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]
ST_3 : Operation 90 [1/1] (0.00ns)   --->   "%crop_0_1_load_1 = load float* %crop_0_1"
ST_3 : Operation 91 [1/1] (0.00ns)   --->   "%crop_1_0_load = load float* %crop_1_0" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]
ST_3 : Operation 92 [1/1] (0.00ns)   --->   "%crop_1_1_load_1 = load float* %crop_1_1"
ST_3 : Operation 93 [1/1] (0.00ns)   --->   "%crop_2_0_load = load float* %crop_2_0" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]
ST_3 : Operation 94 [1/1] (0.00ns)   --->   "%crop_2_1_load_1 = load float* %crop_2_1"
ST_3 : Operation 95 [1/1] (0.00ns)   --->   "store float %crop_2_1_load_1, float* %crop_2_0"
ST_3 : Operation 96 [1/1] (0.00ns)   --->   "store float %crop_1_1_load_1, float* %crop_1_0"
ST_3 : Operation 97 [1/1] (0.00ns)   --->   "store float %crop_0_1_load_1, float* %crop_0_0"
ST_3 : Operation 98 [1/1] (0.00ns)   --->   "br i1 %exitcond_flatten, label %3, label %.reset"
ST_3 : Operation 99 [1/1] (0.00ns)   --->   "%crop_0_1_load = load float* %crop_0_1" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]
ST_3 : Operation 100 [1/1] (0.00ns)   --->   "%crop_1_1_load = load float* %crop_1_1" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]
ST_3 : Operation 101 [1/1] (0.00ns)   --->   "%crop_2_1_load = load float* %crop_2_1" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]
ST_3 : Operation 102 [1/1] (3.63ns)   --->   "%tmp_5 = call float @_ssdm_op_Read.ap_fifo.volatile.floatP(float* %in_stream_V)" [edge_detection/edge_detection.cpp:59]   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_3 : Operation 103 [1/2] (2.32ns)   --->   "%crop_0_2 = load float* %temp_array_0_assign_1, align 4" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_3 : Operation 104 [1/2] (2.32ns)   --->   "%crop_1_2 = load float* %temp_array_1_assign_1, align 4" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_3 : Operation 105 [1/1] (2.32ns)   --->   "store float %crop_1_2, float* %temp_array_0_assign_1, align 4" [edge_detection/edge_detection.cpp:33->edge_detection/edge_detection.cpp:60]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_3 : Operation 106 [1/1] (2.32ns)   --->   "store float %tmp_5, float* %temp_array_1_assign_1, align 4" [edge_detection/edge_detection.cpp:34->edge_detection/edge_detection.cpp:60]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 20> <RAM>
ST_3 : Operation 107 [4/4] (5.70ns)   --->   "%tmp_4_0_i = fmul float %crop_0_0_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 108 [1/1] (0.00ns)   --->   "store float %tmp_5, float* %crop_2_1" [edge_detection/edge_detection.cpp:59]
ST_3 : Operation 109 [1/1] (0.00ns)   --->   "store float %crop_1_2, float* %crop_1_1" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]
ST_3 : Operation 110 [1/1] (0.00ns)   --->   "store float %crop_0_2, float* %crop_0_1" [edge_detection/edge_detection.cpp:29->edge_detection/edge_detection.cpp:60]

 <State 4> : 5.70ns
ST_4 : Operation 111 [3/4] (5.70ns)   --->   "%tmp_4_0_i = fmul float %crop_0_0_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 5> : 5.70ns
ST_5 : Operation 112 [2/4] (5.70ns)   --->   "%tmp_4_0_i = fmul float %crop_0_0_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 6> : 5.70ns
ST_6 : Operation 113 [1/4] (5.70ns)   --->   "%tmp_4_0_i = fmul float %crop_0_0_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 7> : 7.26ns
ST_7 : Operation 114 [5/5] (7.25ns)   --->   "%result_2_0_i = fadd float %tmp_4_0_i, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 8> : 7.26ns
ST_8 : Operation 115 [4/5] (7.25ns)   --->   "%result_2_0_i = fadd float %tmp_4_0_i, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 9> : 7.26ns
ST_9 : Operation 116 [3/5] (7.25ns)   --->   "%result_2_0_i = fadd float %tmp_4_0_i, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 10> : 7.26ns
ST_10 : Operation 117 [2/5] (7.25ns)   --->   "%result_2_0_i = fadd float %tmp_4_0_i, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 11> : 7.26ns
ST_11 : Operation 118 [1/5] (7.25ns)   --->   "%result_2_0_i = fadd float %tmp_4_0_i, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 12> : 7.26ns
ST_12 : Operation 119 [5/5] (7.25ns)   --->   "%result_2_0_1_i = fadd float %result_2_0_i, %crop_0_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 13> : 7.26ns
ST_13 : Operation 120 [4/5] (7.25ns)   --->   "%result_2_0_1_i = fadd float %result_2_0_i, %crop_0_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_13 : Operation 121 [4/4] (5.70ns)   --->   "%tmp_4_0_2_i = fmul float %crop_0_2, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 14> : 7.26ns
ST_14 : Operation 122 [3/5] (7.25ns)   --->   "%result_2_0_1_i = fadd float %result_2_0_i, %crop_0_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_14 : Operation 123 [3/4] (5.70ns)   --->   "%tmp_4_0_2_i = fmul float %crop_0_2, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 15> : 7.26ns
ST_15 : Operation 124 [2/5] (7.25ns)   --->   "%result_2_0_1_i = fadd float %result_2_0_i, %crop_0_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_15 : Operation 125 [2/4] (5.70ns)   --->   "%tmp_4_0_2_i = fmul float %crop_0_2, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 16> : 7.26ns
ST_16 : Operation 126 [1/5] (7.25ns)   --->   "%result_2_0_1_i = fadd float %result_2_0_i, %crop_0_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_16 : Operation 127 [1/4] (5.70ns)   --->   "%tmp_4_0_2_i = fmul float %crop_0_2, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 17> : 7.26ns
ST_17 : Operation 128 [5/5] (7.25ns)   --->   "%result_2_0_2_i = fadd float %result_2_0_1_i, %tmp_4_0_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 18> : 7.26ns
ST_18 : Operation 129 [4/5] (7.25ns)   --->   "%result_2_0_2_i = fadd float %result_2_0_1_i, %tmp_4_0_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 19> : 7.26ns
ST_19 : Operation 130 [3/5] (7.25ns)   --->   "%result_2_0_2_i = fadd float %result_2_0_1_i, %tmp_4_0_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 20> : 7.26ns
ST_20 : Operation 131 [2/5] (7.25ns)   --->   "%result_2_0_2_i = fadd float %result_2_0_1_i, %tmp_4_0_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 21> : 7.26ns
ST_21 : Operation 132 [1/5] (7.25ns)   --->   "%result_2_0_2_i = fadd float %result_2_0_1_i, %tmp_4_0_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 22> : 7.26ns
ST_22 : Operation 133 [5/5] (7.25ns)   --->   "%result_2_1_i = fadd float %result_2_0_2_i, %crop_1_0_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 23> : 7.26ns
ST_23 : Operation 134 [4/5] (7.25ns)   --->   "%result_2_1_i = fadd float %result_2_0_2_i, %crop_1_0_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_23 : Operation 135 [4/4] (5.70ns)   --->   "%tmp_4_1_1_i = fmul float %crop_1_1_load, -4.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 24> : 7.26ns
ST_24 : Operation 136 [3/5] (7.25ns)   --->   "%result_2_1_i = fadd float %result_2_0_2_i, %crop_1_0_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_24 : Operation 137 [3/4] (5.70ns)   --->   "%tmp_4_1_1_i = fmul float %crop_1_1_load, -4.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 25> : 7.26ns
ST_25 : Operation 138 [2/5] (7.25ns)   --->   "%result_2_1_i = fadd float %result_2_0_2_i, %crop_1_0_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_25 : Operation 139 [2/4] (5.70ns)   --->   "%tmp_4_1_1_i = fmul float %crop_1_1_load, -4.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 26> : 7.26ns
ST_26 : Operation 140 [1/5] (7.25ns)   --->   "%result_2_1_i = fadd float %result_2_0_2_i, %crop_1_0_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_26 : Operation 141 [1/4] (5.70ns)   --->   "%tmp_4_1_1_i = fmul float %crop_1_1_load, -4.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 27> : 7.26ns
ST_27 : Operation 142 [5/5] (7.25ns)   --->   "%result_2_1_1_i = fadd float %result_2_1_i, %tmp_4_1_1_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 28> : 7.26ns
ST_28 : Operation 143 [4/5] (7.25ns)   --->   "%result_2_1_1_i = fadd float %result_2_1_i, %tmp_4_1_1_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 29> : 7.26ns
ST_29 : Operation 144 [3/5] (7.25ns)   --->   "%result_2_1_1_i = fadd float %result_2_1_i, %tmp_4_1_1_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 30> : 7.26ns
ST_30 : Operation 145 [2/5] (7.25ns)   --->   "%result_2_1_1_i = fadd float %result_2_1_i, %tmp_4_1_1_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 31> : 7.26ns
ST_31 : Operation 146 [1/5] (7.25ns)   --->   "%result_2_1_1_i = fadd float %result_2_1_i, %tmp_4_1_1_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 32> : 7.26ns
ST_32 : Operation 147 [5/5] (7.25ns)   --->   "%result_2_1_2_i = fadd float %result_2_1_1_i, %crop_1_2" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 33> : 7.26ns
ST_33 : Operation 148 [4/5] (7.25ns)   --->   "%result_2_1_2_i = fadd float %result_2_1_1_i, %crop_1_2" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_33 : Operation 149 [4/4] (5.70ns)   --->   "%tmp_4_2_i = fmul float %crop_2_0_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 34> : 7.26ns
ST_34 : Operation 150 [3/5] (7.25ns)   --->   "%result_2_1_2_i = fadd float %result_2_1_1_i, %crop_1_2" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_34 : Operation 151 [3/4] (5.70ns)   --->   "%tmp_4_2_i = fmul float %crop_2_0_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 35> : 7.26ns
ST_35 : Operation 152 [2/5] (7.25ns)   --->   "%result_2_1_2_i = fadd float %result_2_1_1_i, %crop_1_2" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_35 : Operation 153 [2/4] (5.70ns)   --->   "%tmp_4_2_i = fmul float %crop_2_0_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 36> : 7.26ns
ST_36 : Operation 154 [1/5] (7.25ns)   --->   "%result_2_1_2_i = fadd float %result_2_1_1_i, %crop_1_2" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_36 : Operation 155 [1/4] (5.70ns)   --->   "%tmp_4_2_i = fmul float %crop_2_0_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 37> : 7.26ns
ST_37 : Operation 156 [5/5] (7.25ns)   --->   "%result_2_2_i = fadd float %result_2_1_2_i, %tmp_4_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 38> : 7.26ns
ST_38 : Operation 157 [4/5] (7.25ns)   --->   "%result_2_2_i = fadd float %result_2_1_2_i, %tmp_4_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 39> : 7.26ns
ST_39 : Operation 158 [3/5] (7.25ns)   --->   "%result_2_2_i = fadd float %result_2_1_2_i, %tmp_4_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 40> : 7.26ns
ST_40 : Operation 159 [2/5] (7.25ns)   --->   "%result_2_2_i = fadd float %result_2_1_2_i, %tmp_4_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 41> : 7.26ns
ST_41 : Operation 160 [1/5] (7.25ns)   --->   "%result_2_2_i = fadd float %result_2_1_2_i, %tmp_4_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 42> : 7.26ns
ST_42 : Operation 161 [5/5] (7.25ns)   --->   "%result_2_2_1_i = fadd float %result_2_2_i, %crop_2_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 43> : 7.26ns
ST_43 : Operation 162 [4/5] (7.25ns)   --->   "%result_2_2_1_i = fadd float %result_2_2_i, %crop_2_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_43 : Operation 163 [4/4] (5.70ns)   --->   "%tmp_4_2_2_i = fmul float %tmp_5, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 44> : 7.26ns
ST_44 : Operation 164 [3/5] (7.25ns)   --->   "%result_2_2_1_i = fadd float %result_2_2_i, %crop_2_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_44 : Operation 165 [3/4] (5.70ns)   --->   "%tmp_4_2_2_i = fmul float %tmp_5, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 45> : 7.26ns
ST_45 : Operation 166 [2/5] (7.25ns)   --->   "%result_2_2_1_i = fadd float %result_2_2_i, %crop_2_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_45 : Operation 167 [2/4] (5.70ns)   --->   "%tmp_4_2_2_i = fmul float %tmp_5, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 46> : 7.26ns
ST_46 : Operation 168 [1/5] (7.25ns)   --->   "%result_2_2_1_i = fadd float %result_2_2_i, %crop_2_1_load" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_46 : Operation 169 [1/4] (5.70ns)   --->   "%tmp_4_2_2_i = fmul float %tmp_5, 0.000000e+00" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 47> : 7.26ns
ST_47 : Operation 170 [5/5] (7.25ns)   --->   "%tmp_4 = fadd float %result_2_2_1_i, %tmp_4_2_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 48> : 7.26ns
ST_48 : Operation 171 [4/5] (7.25ns)   --->   "%tmp_4 = fadd float %result_2_2_1_i, %tmp_4_2_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 49> : 7.26ns
ST_49 : Operation 172 [3/5] (7.25ns)   --->   "%tmp_4 = fadd float %result_2_2_1_i, %tmp_4_2_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 50> : 7.26ns
ST_50 : Operation 173 [2/5] (7.25ns)   --->   "%tmp_4 = fadd float %result_2_2_1_i, %tmp_4_2_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 51> : 7.26ns
ST_51 : Operation 174 [1/5] (7.25ns)   --->   "%tmp_4 = fadd float %result_2_2_1_i, %tmp_4_2_2_i" [edge_detection/edge_detection.cpp:8->edge_detection/edge_detection.cpp:61]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 52> : 3.63ns
ST_52 : Operation 175 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecLoopName([20 x i8]* @conv_rows_conv_cols_s)"
ST_52 : Operation 176 [1/1] (0.00ns)   --->   "%empty_11 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 400, i64 400, i64 400)"
ST_52 : Operation 177 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecLoopName([10 x i8]* @p_str5) nounwind" [edge_detection/edge_detection.cpp:56]
ST_52 : Operation 178 [1/1] (0.00ns)   --->   "%tmp_6 = call i32 (...)* @_ssdm_op_SpecRegionBegin([10 x i8]* @p_str5)" [edge_detection/edge_detection.cpp:56]
ST_52 : Operation 179 [1/1] (0.00ns)   --->   "call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:57]
ST_52 : Operation 180 [1/1] (3.63ns)   --->   "call void @_ssdm_op_Write.ap_fifo.volatile.floatP(float* %out_stream_V, float %tmp_4)" [edge_detection/edge_detection.cpp:63]   --->   Core 32 'FIFO' <Latency = 0> <II = 1> <Delay = 3.63> <Storage> <Opcode : 'read' 'write' 'nbread' 'nbwrite'> <Ports = 0> <Width = 32> <Depth = 2> <FIFO>
ST_52 : Operation 181 [1/1] (0.00ns)   --->   "br label %._crit_edge" [edge_detection/edge_detection.cpp:63]
ST_52 : Operation 182 [1/1] (0.00ns)   --->   "%empty = call i32 (...)* @_ssdm_op_SpecRegionEnd([10 x i8]* @p_str5, i32 %tmp_6)" [edge_detection/edge_detection.cpp:64]
ST_52 : Operation 183 [1/1] (0.00ns)   --->   "br label %1"

 <State 53> : 0.00ns
ST_53 : Operation 184 [1/1] (0.00ns)   --->   "ret void" [edge_detection/edge_detection.cpp:66]


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 0
- Is top level: 0
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ in_stream_V]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
Port [ out_stream_V]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=3; pingpong=0; private_global=0; IO mode=ap_fifo:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
crop_0_0              (alloca           ) [ 001111111111111111111111111111111111111111111111111110]
crop_0_1              (alloca           ) [ 001111111111111111111111111111111111111111111111111110]
crop_1_0              (alloca           ) [ 001111111111111111111111111111111111111111111111111110]
crop_1_1              (alloca           ) [ 001111111111111111111111111111111111111111111111111110]
crop_2_0              (alloca           ) [ 001111111111111111111111111111111111111111111111111110]
crop_2_1              (alloca           ) [ 001111111111111111111111111111111111111111111111111110]
StgValue_60           (specinterface    ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_61           (specinterface    ) [ 000000000000000000000000000000000000000000000000000000]
temp_array_0_assign   (alloca           ) [ 001111111111111111111111111111111111111111111111111110]
temp_array_1_assign   (alloca           ) [ 001111111111111111111111111111111111111111111111111110]
StgValue_64           (br               ) [ 011111111111111111111111111111111111111111111111111110]
indvar_flatten        (phi              ) [ 001000000000000000000000000000000000000000000000000000]
i                     (phi              ) [ 001000000000000000000000000000000000000000000000000000]
pos_y_assign          (phi              ) [ 001000000000000000000000000000000000000000000000000000]
exitcond_flatten      (icmp             ) [ 001111111111111111111111111111111111111111111111111110]
indvar_flatten_next   (add              ) [ 011111111111111111111111111111111111111111111111111110]
exitcond              (icmp             ) [ 000000000000000000000000000000000000000000000000000000]
pos_y_assign_mid2     (select           ) [ 000000000000000000000000000000000000000000000000000000]
i_s                   (add              ) [ 000000000000000000000000000000000000000000000000000000]
tmp                   (partselect       ) [ 000000000000000000000000000000000000000000000000000000]
icmp                  (icmp             ) [ 000000000000000000000000000000000000000000000000000000]
tmp_1                 (partselect       ) [ 000000000000000000000000000000000000000000000000000000]
icmp1                 (icmp             ) [ 000000000000000000000000000000000000000000000000000000]
tmp_mid2              (select           ) [ 000000000000000000000000000000000000000000000000000000]
i_mid2                (select           ) [ 011111111111111111111111111111111111111111111111111110]
tmp_i                 (zext             ) [ 000000000000000000000000000000000000000000000000000000]
temp_array_0_assign_1 (getelementptr    ) [ 001100000000000000000000000000000000000000000000000000]
temp_array_1_assign_1 (getelementptr    ) [ 001100000000000000000000000000000000000000000000000000]
tmp_3                 (partselect       ) [ 000000000000000000000000000000000000000000000000000000]
icmp2                 (icmp             ) [ 000000000000000000000000000000000000000000000000000000]
or_cond               (and              ) [ 001111111111111111111111111111111111111111111111111110]
StgValue_87           (br               ) [ 000000000000000000000000000000000000000000000000000000]
j                     (add              ) [ 011111111111111111111111111111111111111111111111111110]
crop_0_0_load         (load             ) [ 001011100000000000000000000000000000000000000000000000]
crop_0_1_load_1       (load             ) [ 000000000000000000000000000000000000000000000000000000]
crop_1_0_load         (load             ) [ 001011111111111111111111111000000000000000000000000000]
crop_1_1_load_1       (load             ) [ 000000000000000000000000000000000000000000000000000000]
crop_2_0_load         (load             ) [ 001011111111111111111111111111111111100000000000000000]
crop_2_1_load_1       (load             ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_95           (store            ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_96           (store            ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_97           (store            ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_98           (br               ) [ 000000000000000000000000000000000000000000000000000000]
crop_0_1_load         (load             ) [ 001011111111111110000000000000000000000000000000000000]
crop_1_1_load         (load             ) [ 001011111111111111111111111000000000000000000000000000]
crop_2_1_load         (load             ) [ 001011111111111111111111111111111111111111111110000000]
tmp_5                 (read             ) [ 001011111111111111111111111111111111111111111110000000]
crop_0_2              (load             ) [ 001011111111111110000000000000000000000000000000000000]
crop_1_2              (load             ) [ 001011111111111111111111111111111111100000000000000000]
StgValue_105          (store            ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_106          (store            ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_108          (store            ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_109          (store            ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_110          (store            ) [ 000000000000000000000000000000000000000000000000000000]
tmp_4_0_i             (fmul             ) [ 001000011111000000000000000000000000000000000000000000]
result_2_0_i          (fadd             ) [ 001000000000111110000000000000000000000000000000000000]
result_2_0_1_i        (fadd             ) [ 001000000000000001111100000000000000000000000000000000]
tmp_4_0_2_i           (fmul             ) [ 001000000000000001111100000000000000000000000000000000]
result_2_0_2_i        (fadd             ) [ 001000000000000000000011111000000000000000000000000000]
result_2_1_i          (fadd             ) [ 001000000000000000000000000111110000000000000000000000]
tmp_4_1_1_i           (fmul             ) [ 001000000000000000000000000111110000000000000000000000]
result_2_1_1_i        (fadd             ) [ 001000000000000000000000000000001111100000000000000000]
result_2_1_2_i        (fadd             ) [ 001000000000000000000000000000000000011111000000000000]
tmp_4_2_i             (fmul             ) [ 001000000000000000000000000000000000011111000000000000]
result_2_2_i          (fadd             ) [ 001000000000000000000000000000000000000000111110000000]
result_2_2_1_i        (fadd             ) [ 001000000000000000000000000000000000000000000001111100]
tmp_4_2_2_i           (fmul             ) [ 001000000000000000000000000000000000000000000001111100]
tmp_4                 (fadd             ) [ 001000000000000000000000000000000000000000000000000010]
StgValue_175          (specloopname     ) [ 000000000000000000000000000000000000000000000000000000]
empty_11              (speclooptripcount) [ 000000000000000000000000000000000000000000000000000000]
StgValue_177          (specloopname     ) [ 000000000000000000000000000000000000000000000000000000]
tmp_6                 (specregionbegin  ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_179          (specpipeline     ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_180          (write            ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_181          (br               ) [ 000000000000000000000000000000000000000000000000000000]
empty                 (specregionend    ) [ 000000000000000000000000000000000000000000000000000000]
StgValue_183          (br               ) [ 011111111111111111111111111111111111111111111111111110]
StgValue_184          (ret              ) [ 000000000000000000000000000000000000000000000000000000]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="in_stream_V">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="in_stream_V"/></StgValue>
</bind>
</comp>

<comp id="2" class="1000" name="out_stream_V">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="out_stream_V"/></StgValue>
</bind>
</comp>

<comp id="4" class="1001" name="const_4">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="6" class="1001" name="const_6">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecInterface"/></StgValue>
</bind>
</comp>

<comp id="8" class="1001" name="const_8">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="ap_fifo_str"/></StgValue>
</bind>
</comp>

<comp id="10" class="1001" name="const_10">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str44"/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str45"/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str46"/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str47"/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="24" class="1001" name="const_24">
<pin_list>
<pin id="25" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str48"/></StgValue>
</bind>
</comp>

<comp id="26" class="1001" name="const_26">
<pin_list>
<pin id="27" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str49"/></StgValue>
</bind>
</comp>

<comp id="28" class="1001" name="const_28">
<pin_list>
<pin id="29" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str37"/></StgValue>
</bind>
</comp>

<comp id="30" class="1001" name="const_30">
<pin_list>
<pin id="31" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str38"/></StgValue>
</bind>
</comp>

<comp id="32" class="1001" name="const_32">
<pin_list>
<pin id="33" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str39"/></StgValue>
</bind>
</comp>

<comp id="34" class="1001" name="const_34">
<pin_list>
<pin id="35" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str40"/></StgValue>
</bind>
</comp>

<comp id="36" class="1001" name="const_36">
<pin_list>
<pin id="37" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str41"/></StgValue>
</bind>
</comp>

<comp id="38" class="1001" name="const_38">
<pin_list>
<pin id="39" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str42"/></StgValue>
</bind>
</comp>

<comp id="40" class="1001" name="const_40">
<pin_list>
<pin id="41" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="42" class="1001" name="const_42">
<pin_list>
<pin id="43" dir="1" index="0" bw="1" slack="1"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="44" class="1001" name="const_44">
<pin_list>
<pin id="45" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="46" class="1001" name="const_46">
<pin_list>
<pin id="47" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="48" class="1001" name="const_48">
<pin_list>
<pin id="49" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="50" class="1001" name="const_50">
<pin_list>
<pin id="51" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="52" class="1001" name="const_52">
<pin_list>
<pin id="53" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="54" class="1001" name="const_54">
<pin_list>
<pin id="55" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_PartSelect.i4.i5.i32.i32"/></StgValue>
</bind>
</comp>

<comp id="56" class="1001" name="const_56">
<pin_list>
<pin id="57" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="58" class="1001" name="const_58">
<pin_list>
<pin id="59" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="60" class="1001" name="const_60">
<pin_list>
<pin id="61" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="62" class="1001" name="const_62">
<pin_list>
<pin id="63" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Read.ap_fifo.volatile.floatP"/></StgValue>
</bind>
</comp>

<comp id="64" class="1001" name="const_64">
<pin_list>
<pin id="65" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="66" class="1001" name="const_66">
<pin_list>
<pin id="67" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="68" class="1001" name="const_68">
<pin_list>
<pin id="69" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopName"/></StgValue>
</bind>
</comp>

<comp id="70" class="1001" name="const_70">
<pin_list>
<pin id="71" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="conv_rows_conv_cols_s"/></StgValue>
</bind>
</comp>

<comp id="72" class="1001" name="const_72">
<pin_list>
<pin id="73" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecLoopTripCount"/></StgValue>
</bind>
</comp>

<comp id="74" class="1001" name="const_74">
<pin_list>
<pin id="75" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="76" class="1001" name="const_76">
<pin_list>
<pin id="77" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str5"/></StgValue>
</bind>
</comp>

<comp id="78" class="1001" name="const_78">
<pin_list>
<pin id="79" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionBegin"/></StgValue>
</bind>
</comp>

<comp id="80" class="1001" name="const_80">
<pin_list>
<pin id="81" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecPipeline"/></StgValue>
</bind>
</comp>

<comp id="82" class="1001" name="const_82">
<pin_list>
<pin id="83" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="84" class="1001" name="const_84">
<pin_list>
<pin id="85" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="p_str1"/></StgValue>
</bind>
</comp>

<comp id="86" class="1001" name="const_86">
<pin_list>
<pin id="87" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_Write.ap_fifo.volatile.floatP"/></StgValue>
</bind>
</comp>

<comp id="88" class="1001" name="const_88">
<pin_list>
<pin id="89" dir="1" index="0" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<StgValue><ssdm name="_ssdm_op_SpecRegionEnd"/></StgValue>
</bind>
</comp>

<comp id="90" class="1004" name="crop_0_0_fu_90">
<pin_list>
<pin id="91" dir="0" index="0" bw="1" slack="0"/>
<pin id="92" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="crop_0_0/1 "/>
</bind>
</comp>

<comp id="94" class="1004" name="crop_0_1_fu_94">
<pin_list>
<pin id="95" dir="0" index="0" bw="1" slack="0"/>
<pin id="96" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="crop_0_1/1 "/>
</bind>
</comp>

<comp id="98" class="1004" name="crop_1_0_fu_98">
<pin_list>
<pin id="99" dir="0" index="0" bw="1" slack="0"/>
<pin id="100" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="crop_1_0/1 "/>
</bind>
</comp>

<comp id="102" class="1004" name="crop_1_1_fu_102">
<pin_list>
<pin id="103" dir="0" index="0" bw="1" slack="0"/>
<pin id="104" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="crop_1_1/1 "/>
</bind>
</comp>

<comp id="106" class="1004" name="crop_2_0_fu_106">
<pin_list>
<pin id="107" dir="0" index="0" bw="1" slack="0"/>
<pin id="108" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="crop_2_0/1 "/>
</bind>
</comp>

<comp id="110" class="1004" name="crop_2_1_fu_110">
<pin_list>
<pin id="111" dir="0" index="0" bw="1" slack="0"/>
<pin id="112" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="crop_2_1/1 "/>
</bind>
</comp>

<comp id="114" class="1004" name="temp_array_0_assign_alloca_fu_114">
<pin_list>
<pin id="115" dir="0" index="0" bw="1" slack="0"/>
<pin id="116" dir="1" index="1" bw="32" slack="2147483647"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="temp_array_0_assign/1 "/>
</bind>
</comp>

<comp id="118" class="1004" name="temp_array_1_assign_alloca_fu_118">
<pin_list>
<pin id="119" dir="0" index="0" bw="1" slack="0"/>
<pin id="120" dir="1" index="1" bw="32" slack="2147483647"/>
</pin_list>
<bind>
<opcode="alloca(26) " fcode="alloca"/>
<opset="temp_array_1_assign/1 "/>
</bind>
</comp>

<comp id="122" class="1004" name="tmp_5_read_fu_122">
<pin_list>
<pin id="123" dir="0" index="0" bw="32" slack="0"/>
<pin id="124" dir="0" index="1" bw="32" slack="0"/>
<pin id="125" dir="1" index="2" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="read(1150) " fcode="read"/>
<opset="tmp_5/3 "/>
</bind>
</comp>

<comp id="128" class="1004" name="StgValue_180_write_fu_128">
<pin_list>
<pin id="129" dir="0" index="0" bw="0" slack="0"/>
<pin id="130" dir="0" index="1" bw="32" slack="0"/>
<pin id="131" dir="0" index="2" bw="32" slack="1"/>
<pin id="132" dir="1" index="3" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="write(1151) " fcode="write"/>
<opset="StgValue_180/52 "/>
</bind>
</comp>

<comp id="135" class="1004" name="temp_array_0_assign_1_gep_fu_135">
<pin_list>
<pin id="136" dir="0" index="0" bw="32" slack="2147483647"/>
<pin id="137" dir="0" index="1" bw="1" slack="0"/>
<pin id="138" dir="0" index="2" bw="5" slack="0"/>
<pin id="139" dir="1" index="3" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="temp_array_0_assign_1/2 "/>
</bind>
</comp>

<comp id="141" class="1004" name="grp_access_fu_141">
<pin_list>
<pin id="142" dir="0" index="0" bw="5" slack="0"/>
<pin id="143" dir="0" index="1" bw="32" slack="2147483647"/>
<pin id="157" dir="0" index="3" bw="5" slack="1"/>
<pin id="158" dir="0" index="4" bw="32" slack="0"/>
<pin id="144" dir="1" index="2" bw="32" slack="0"/>
<pin id="159" dir="1" index="5" bw="32" slack="2147483647"/>
</pin_list>
<bind>
<opcode="load(27) store(28) " fcode="store"/>
<opset="crop_0_2/2 StgValue_105/3 "/>
</bind>
</comp>

<comp id="146" class="1004" name="temp_array_1_assign_1_gep_fu_146">
<pin_list>
<pin id="147" dir="0" index="0" bw="32" slack="2147483647"/>
<pin id="148" dir="0" index="1" bw="1" slack="0"/>
<pin id="149" dir="0" index="2" bw="5" slack="0"/>
<pin id="150" dir="1" index="3" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="temp_array_1_assign_1/2 "/>
</bind>
</comp>

<comp id="152" class="1004" name="grp_access_fu_152">
<pin_list>
<pin id="153" dir="0" index="0" bw="5" slack="0"/>
<pin id="154" dir="0" index="1" bw="32" slack="2147483647"/>
<pin id="161" dir="0" index="3" bw="5" slack="1"/>
<pin id="162" dir="0" index="4" bw="32" slack="0"/>
<pin id="155" dir="1" index="2" bw="32" slack="0"/>
<pin id="163" dir="1" index="5" bw="32" slack="2147483647"/>
</pin_list>
<bind>
<opcode="load(27) store(28) " fcode="store"/>
<opset="crop_1_2/2 StgValue_106/3 "/>
</bind>
</comp>

<comp id="165" class="1005" name="indvar_flatten_reg_165">
<pin_list>
<pin id="166" dir="0" index="0" bw="9" slack="1"/>
<pin id="167" dir="1" index="1" bw="9" slack="1"/>
</pin_list>
<bind>
<opset="indvar_flatten (phireg) "/>
</bind>
</comp>

<comp id="169" class="1004" name="indvar_flatten_phi_fu_169">
<pin_list>
<pin id="170" dir="0" index="0" bw="1" slack="1"/>
<pin id="171" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="172" dir="0" index="2" bw="9" slack="0"/>
<pin id="173" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="174" dir="1" index="4" bw="9" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="indvar_flatten/2 "/>
</bind>
</comp>

<comp id="176" class="1005" name="i_reg_176">
<pin_list>
<pin id="177" dir="0" index="0" bw="5" slack="1"/>
<pin id="178" dir="1" index="1" bw="5" slack="1"/>
</pin_list>
<bind>
<opset="i (phireg) "/>
</bind>
</comp>

<comp id="180" class="1004" name="i_phi_fu_180">
<pin_list>
<pin id="181" dir="0" index="0" bw="1" slack="1"/>
<pin id="182" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="183" dir="0" index="2" bw="5" slack="0"/>
<pin id="184" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="185" dir="1" index="4" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="i/2 "/>
</bind>
</comp>

<comp id="187" class="1005" name="pos_y_assign_reg_187">
<pin_list>
<pin id="188" dir="0" index="0" bw="5" slack="1"/>
<pin id="189" dir="1" index="1" bw="5" slack="1"/>
</pin_list>
<bind>
<opset="pos_y_assign (phireg) "/>
</bind>
</comp>

<comp id="191" class="1004" name="pos_y_assign_phi_fu_191">
<pin_list>
<pin id="192" dir="0" index="0" bw="1" slack="1"/>
<pin id="193" dir="0" index="1" bw="0" slack="2147483647"/>
<pin id="194" dir="0" index="2" bw="5" slack="0"/>
<pin id="195" dir="0" index="3" bw="0" slack="2147483647"/>
<pin id="196" dir="1" index="4" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="phi(47) " fcode="phi"/>
<opset="pos_y_assign/2 "/>
</bind>
</comp>

<comp id="198" class="1004" name="grp_fu_198">
<pin_list>
<pin id="199" dir="0" index="0" bw="32" slack="1"/>
<pin id="200" dir="0" index="1" bw="32" slack="0"/>
<pin id="201" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_0_i/7 "/>
</bind>
</comp>

<comp id="203" class="1004" name="grp_fu_203">
<pin_list>
<pin id="204" dir="0" index="0" bw="32" slack="1"/>
<pin id="205" dir="0" index="1" bw="32" slack="9"/>
<pin id="206" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_0_1_i/12 "/>
</bind>
</comp>

<comp id="207" class="1004" name="grp_fu_207">
<pin_list>
<pin id="208" dir="0" index="0" bw="32" slack="1"/>
<pin id="209" dir="0" index="1" bw="32" slack="1"/>
<pin id="210" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_0_2_i/17 "/>
</bind>
</comp>

<comp id="211" class="1004" name="grp_fu_211">
<pin_list>
<pin id="212" dir="0" index="0" bw="32" slack="1"/>
<pin id="213" dir="0" index="1" bw="32" slack="19"/>
<pin id="214" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_1_i/22 "/>
</bind>
</comp>

<comp id="215" class="1004" name="grp_fu_215">
<pin_list>
<pin id="216" dir="0" index="0" bw="32" slack="1"/>
<pin id="217" dir="0" index="1" bw="32" slack="1"/>
<pin id="218" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_1_1_i/27 "/>
</bind>
</comp>

<comp id="219" class="1004" name="grp_fu_219">
<pin_list>
<pin id="220" dir="0" index="0" bw="32" slack="1"/>
<pin id="221" dir="0" index="1" bw="32" slack="29"/>
<pin id="222" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_1_2_i/32 "/>
</bind>
</comp>

<comp id="223" class="1004" name="grp_fu_223">
<pin_list>
<pin id="224" dir="0" index="0" bw="32" slack="1"/>
<pin id="225" dir="0" index="1" bw="32" slack="1"/>
<pin id="226" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_2_i/37 "/>
</bind>
</comp>

<comp id="227" class="1004" name="grp_fu_227">
<pin_list>
<pin id="228" dir="0" index="0" bw="32" slack="1"/>
<pin id="229" dir="0" index="1" bw="32" slack="39"/>
<pin id="230" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_2_1_i/42 "/>
</bind>
</comp>

<comp id="231" class="1004" name="grp_fu_231">
<pin_list>
<pin id="232" dir="0" index="0" bw="32" slack="1"/>
<pin id="233" dir="0" index="1" bw="32" slack="1"/>
<pin id="234" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="tmp_4/47 "/>
</bind>
</comp>

<comp id="235" class="1004" name="grp_fu_235">
<pin_list>
<pin id="236" dir="0" index="0" bw="32" slack="0"/>
<pin id="237" dir="0" index="1" bw="32" slack="0"/>
<pin id="238" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fmul(13) " fcode="fmul"/>
<opset="tmp_4_0_i/3 "/>
</bind>
</comp>

<comp id="240" class="1004" name="grp_fu_240">
<pin_list>
<pin id="241" dir="0" index="0" bw="32" slack="10"/>
<pin id="242" dir="0" index="1" bw="32" slack="0"/>
<pin id="243" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fmul(13) " fcode="fmul"/>
<opset="tmp_4_0_2_i/13 "/>
</bind>
</comp>

<comp id="245" class="1004" name="grp_fu_245">
<pin_list>
<pin id="246" dir="0" index="0" bw="32" slack="20"/>
<pin id="247" dir="0" index="1" bw="32" slack="0"/>
<pin id="248" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fmul(13) " fcode="fmul"/>
<opset="tmp_4_1_1_i/23 "/>
</bind>
</comp>

<comp id="250" class="1004" name="grp_fu_250">
<pin_list>
<pin id="251" dir="0" index="0" bw="32" slack="30"/>
<pin id="252" dir="0" index="1" bw="32" slack="0"/>
<pin id="253" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fmul(13) " fcode="fmul"/>
<opset="tmp_4_2_i/33 "/>
</bind>
</comp>

<comp id="255" class="1004" name="grp_fu_255">
<pin_list>
<pin id="256" dir="0" index="0" bw="32" slack="40"/>
<pin id="257" dir="0" index="1" bw="32" slack="0"/>
<pin id="258" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fmul(13) " fcode="fmul"/>
<opset="tmp_4_2_2_i/43 "/>
</bind>
</comp>

<comp id="260" class="1004" name="exitcond_flatten_fu_260">
<pin_list>
<pin id="261" dir="0" index="0" bw="9" slack="0"/>
<pin id="262" dir="0" index="1" bw="8" slack="0"/>
<pin id="263" dir="1" index="2" bw="1" slack="1"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond_flatten/2 "/>
</bind>
</comp>

<comp id="266" class="1004" name="indvar_flatten_next_fu_266">
<pin_list>
<pin id="267" dir="0" index="0" bw="9" slack="0"/>
<pin id="268" dir="0" index="1" bw="1" slack="0"/>
<pin id="269" dir="1" index="2" bw="9" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="indvar_flatten_next/2 "/>
</bind>
</comp>

<comp id="272" class="1004" name="exitcond_fu_272">
<pin_list>
<pin id="273" dir="0" index="0" bw="5" slack="0"/>
<pin id="274" dir="0" index="1" bw="5" slack="0"/>
<pin id="275" dir="1" index="2" bw="1" slack="0"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="exitcond/2 "/>
</bind>
</comp>

<comp id="278" class="1004" name="pos_y_assign_mid2_fu_278">
<pin_list>
<pin id="279" dir="0" index="0" bw="1" slack="0"/>
<pin id="280" dir="0" index="1" bw="1" slack="0"/>
<pin id="281" dir="0" index="2" bw="5" slack="0"/>
<pin id="282" dir="1" index="3" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="select(49) " fcode="select"/>
<opset="pos_y_assign_mid2/2 "/>
</bind>
</comp>

<comp id="286" class="1004" name="i_s_fu_286">
<pin_list>
<pin id="287" dir="0" index="0" bw="5" slack="0"/>
<pin id="288" dir="0" index="1" bw="1" slack="0"/>
<pin id="289" dir="1" index="2" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="i_s/2 "/>
</bind>
</comp>

<comp id="292" class="1004" name="tmp_fu_292">
<pin_list>
<pin id="293" dir="0" index="0" bw="4" slack="0"/>
<pin id="294" dir="0" index="1" bw="5" slack="0"/>
<pin id="295" dir="0" index="2" bw="1" slack="0"/>
<pin id="296" dir="0" index="3" bw="4" slack="0"/>
<pin id="297" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="tmp/2 "/>
</bind>
</comp>

<comp id="302" class="1004" name="icmp_fu_302">
<pin_list>
<pin id="303" dir="0" index="0" bw="4" slack="0"/>
<pin id="304" dir="0" index="1" bw="1" slack="0"/>
<pin id="305" dir="1" index="2" bw="1" slack="0"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="icmp/2 "/>
</bind>
</comp>

<comp id="308" class="1004" name="tmp_1_fu_308">
<pin_list>
<pin id="309" dir="0" index="0" bw="4" slack="0"/>
<pin id="310" dir="0" index="1" bw="5" slack="0"/>
<pin id="311" dir="0" index="2" bw="1" slack="0"/>
<pin id="312" dir="0" index="3" bw="4" slack="0"/>
<pin id="313" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="tmp_1/2 "/>
</bind>
</comp>

<comp id="318" class="1004" name="icmp1_fu_318">
<pin_list>
<pin id="319" dir="0" index="0" bw="4" slack="0"/>
<pin id="320" dir="0" index="1" bw="1" slack="0"/>
<pin id="321" dir="1" index="2" bw="1" slack="0"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="icmp1/2 "/>
</bind>
</comp>

<comp id="324" class="1004" name="tmp_mid2_fu_324">
<pin_list>
<pin id="325" dir="0" index="0" bw="1" slack="0"/>
<pin id="326" dir="0" index="1" bw="1" slack="0"/>
<pin id="327" dir="0" index="2" bw="1" slack="0"/>
<pin id="328" dir="1" index="3" bw="1" slack="0"/>
</pin_list>
<bind>
<opcode="select(49) " fcode="select"/>
<opset="tmp_mid2/2 "/>
</bind>
</comp>

<comp id="332" class="1004" name="i_mid2_fu_332">
<pin_list>
<pin id="333" dir="0" index="0" bw="1" slack="0"/>
<pin id="334" dir="0" index="1" bw="5" slack="0"/>
<pin id="335" dir="0" index="2" bw="5" slack="0"/>
<pin id="336" dir="1" index="3" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="select(49) " fcode="select"/>
<opset="i_mid2/2 "/>
</bind>
</comp>

<comp id="340" class="1004" name="tmp_i_fu_340">
<pin_list>
<pin id="341" dir="0" index="0" bw="5" slack="0"/>
<pin id="342" dir="1" index="1" bw="64" slack="0"/>
</pin_list>
<bind>
<opcode="zext(34) " fcode="zext"/>
<opset="tmp_i/2 "/>
</bind>
</comp>

<comp id="346" class="1004" name="tmp_3_fu_346">
<pin_list>
<pin id="347" dir="0" index="0" bw="4" slack="0"/>
<pin id="348" dir="0" index="1" bw="5" slack="0"/>
<pin id="349" dir="0" index="2" bw="1" slack="0"/>
<pin id="350" dir="0" index="3" bw="4" slack="0"/>
<pin id="351" dir="1" index="4" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="partselect(1002) " fcode="partselect"/>
<opset="tmp_3/2 "/>
</bind>
</comp>

<comp id="356" class="1004" name="icmp2_fu_356">
<pin_list>
<pin id="357" dir="0" index="0" bw="4" slack="0"/>
<pin id="358" dir="0" index="1" bw="1" slack="0"/>
<pin id="359" dir="1" index="2" bw="1" slack="0"/>
</pin_list>
<bind>
<opcode="icmp(45) " fcode="icmp"/>
<opset="icmp2/2 "/>
</bind>
</comp>

<comp id="362" class="1004" name="or_cond_fu_362">
<pin_list>
<pin id="363" dir="0" index="0" bw="1" slack="0"/>
<pin id="364" dir="0" index="1" bw="1" slack="0"/>
<pin id="365" dir="1" index="2" bw="1" slack="50"/>
</pin_list>
<bind>
<opcode="and(23) " fcode="and"/>
<opset="or_cond/2 "/>
</bind>
</comp>

<comp id="368" class="1004" name="j_fu_368">
<pin_list>
<pin id="369" dir="0" index="0" bw="5" slack="0"/>
<pin id="370" dir="0" index="1" bw="1" slack="0"/>
<pin id="371" dir="1" index="2" bw="5" slack="0"/>
</pin_list>
<bind>
<opcode="add(8) " fcode="add"/>
<opset="j/2 "/>
</bind>
</comp>

<comp id="374" class="1004" name="crop_0_0_load_load_fu_374">
<pin_list>
<pin id="375" dir="0" index="0" bw="32" slack="2"/>
<pin id="376" dir="1" index="1" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_0_0_load/3 "/>
</bind>
</comp>

<comp id="378" class="1004" name="crop_0_1_load_1_load_fu_378">
<pin_list>
<pin id="379" dir="0" index="0" bw="32" slack="2"/>
<pin id="380" dir="1" index="1" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_0_1_load_1/3 "/>
</bind>
</comp>

<comp id="381" class="1004" name="crop_1_0_load_load_fu_381">
<pin_list>
<pin id="382" dir="0" index="0" bw="32" slack="2"/>
<pin id="383" dir="1" index="1" bw="32" slack="19"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_1_0_load/3 "/>
</bind>
</comp>

<comp id="384" class="1004" name="crop_1_1_load_1_load_fu_384">
<pin_list>
<pin id="385" dir="0" index="0" bw="32" slack="2"/>
<pin id="386" dir="1" index="1" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_1_1_load_1/3 "/>
</bind>
</comp>

<comp id="387" class="1004" name="crop_2_0_load_load_fu_387">
<pin_list>
<pin id="388" dir="0" index="0" bw="32" slack="2"/>
<pin id="389" dir="1" index="1" bw="32" slack="30"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_2_0_load/3 "/>
</bind>
</comp>

<comp id="390" class="1004" name="crop_2_1_load_1_load_fu_390">
<pin_list>
<pin id="391" dir="0" index="0" bw="32" slack="2"/>
<pin id="392" dir="1" index="1" bw="32" slack="0"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_2_1_load_1/3 "/>
</bind>
</comp>

<comp id="393" class="1004" name="StgValue_95_store_fu_393">
<pin_list>
<pin id="394" dir="0" index="0" bw="32" slack="0"/>
<pin id="395" dir="0" index="1" bw="32" slack="2"/>
<pin id="396" dir="1" index="2" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="store(28) " fcode="store"/>
<opset="StgValue_95/3 "/>
</bind>
</comp>

<comp id="398" class="1004" name="StgValue_96_store_fu_398">
<pin_list>
<pin id="399" dir="0" index="0" bw="32" slack="0"/>
<pin id="400" dir="0" index="1" bw="32" slack="2"/>
<pin id="401" dir="1" index="2" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="store(28) " fcode="store"/>
<opset="StgValue_96/3 "/>
</bind>
</comp>

<comp id="403" class="1004" name="StgValue_97_store_fu_403">
<pin_list>
<pin id="404" dir="0" index="0" bw="32" slack="0"/>
<pin id="405" dir="0" index="1" bw="32" slack="2"/>
<pin id="406" dir="1" index="2" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="store(28) " fcode="store"/>
<opset="StgValue_97/3 "/>
</bind>
</comp>

<comp id="408" class="1004" name="crop_0_1_load_load_fu_408">
<pin_list>
<pin id="409" dir="0" index="0" bw="32" slack="2"/>
<pin id="410" dir="1" index="1" bw="32" slack="9"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_0_1_load/3 "/>
</bind>
</comp>

<comp id="411" class="1004" name="crop_1_1_load_load_fu_411">
<pin_list>
<pin id="412" dir="0" index="0" bw="32" slack="2"/>
<pin id="413" dir="1" index="1" bw="32" slack="20"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_1_1_load/3 "/>
</bind>
</comp>

<comp id="414" class="1004" name="crop_2_1_load_load_fu_414">
<pin_list>
<pin id="415" dir="0" index="0" bw="32" slack="2"/>
<pin id="416" dir="1" index="1" bw="32" slack="39"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="crop_2_1_load/3 "/>
</bind>
</comp>

<comp id="417" class="1004" name="StgValue_108_store_fu_417">
<pin_list>
<pin id="418" dir="0" index="0" bw="32" slack="0"/>
<pin id="419" dir="0" index="1" bw="32" slack="2"/>
<pin id="420" dir="1" index="2" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="store(28) " fcode="store"/>
<opset="StgValue_108/3 "/>
</bind>
</comp>

<comp id="422" class="1004" name="StgValue_109_store_fu_422">
<pin_list>
<pin id="423" dir="0" index="0" bw="32" slack="0"/>
<pin id="424" dir="0" index="1" bw="32" slack="2"/>
<pin id="425" dir="1" index="2" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="store(28) " fcode="store"/>
<opset="StgValue_109/3 "/>
</bind>
</comp>

<comp id="427" class="1004" name="StgValue_110_store_fu_427">
<pin_list>
<pin id="428" dir="0" index="0" bw="32" slack="0"/>
<pin id="429" dir="0" index="1" bw="32" slack="2"/>
<pin id="430" dir="1" index="2" bw="0" slack="2147483647"/>
</pin_list>
<bind>
<opcode="store(28) " fcode="store"/>
<opset="StgValue_110/3 "/>
</bind>
</comp>

<comp id="432" class="1005" name="crop_0_0_reg_432">
<pin_list>
<pin id="433" dir="0" index="0" bw="32" slack="2"/>
<pin id="434" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="crop_0_0 "/>
</bind>
</comp>

<comp id="438" class="1005" name="crop_0_1_reg_438">
<pin_list>
<pin id="439" dir="0" index="0" bw="32" slack="2"/>
<pin id="440" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="crop_0_1 "/>
</bind>
</comp>

<comp id="445" class="1005" name="crop_1_0_reg_445">
<pin_list>
<pin id="446" dir="0" index="0" bw="32" slack="2"/>
<pin id="447" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="crop_1_0 "/>
</bind>
</comp>

<comp id="451" class="1005" name="crop_1_1_reg_451">
<pin_list>
<pin id="452" dir="0" index="0" bw="32" slack="2"/>
<pin id="453" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="crop_1_1 "/>
</bind>
</comp>

<comp id="458" class="1005" name="crop_2_0_reg_458">
<pin_list>
<pin id="459" dir="0" index="0" bw="32" slack="2"/>
<pin id="460" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="crop_2_0 "/>
</bind>
</comp>

<comp id="464" class="1005" name="crop_2_1_reg_464">
<pin_list>
<pin id="465" dir="0" index="0" bw="32" slack="2"/>
<pin id="466" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="crop_2_1 "/>
</bind>
</comp>

<comp id="471" class="1005" name="exitcond_flatten_reg_471">
<pin_list>
<pin id="472" dir="0" index="0" bw="1" slack="1"/>
<pin id="473" dir="1" index="1" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opset="exitcond_flatten "/>
</bind>
</comp>

<comp id="475" class="1005" name="indvar_flatten_next_reg_475">
<pin_list>
<pin id="476" dir="0" index="0" bw="9" slack="0"/>
<pin id="477" dir="1" index="1" bw="9" slack="0"/>
</pin_list>
<bind>
<opset="indvar_flatten_next "/>
</bind>
</comp>

<comp id="480" class="1005" name="i_mid2_reg_480">
<pin_list>
<pin id="481" dir="0" index="0" bw="5" slack="0"/>
<pin id="482" dir="1" index="1" bw="5" slack="0"/>
</pin_list>
<bind>
<opset="i_mid2 "/>
</bind>
</comp>

<comp id="485" class="1005" name="temp_array_0_assign_1_reg_485">
<pin_list>
<pin id="486" dir="0" index="0" bw="5" slack="1"/>
<pin id="487" dir="1" index="1" bw="5" slack="1"/>
</pin_list>
<bind>
<opset="temp_array_0_assign_1 "/>
</bind>
</comp>

<comp id="491" class="1005" name="temp_array_1_assign_1_reg_491">
<pin_list>
<pin id="492" dir="0" index="0" bw="5" slack="1"/>
<pin id="493" dir="1" index="1" bw="5" slack="1"/>
</pin_list>
<bind>
<opset="temp_array_1_assign_1 "/>
</bind>
</comp>

<comp id="497" class="1005" name="or_cond_reg_497">
<pin_list>
<pin id="498" dir="0" index="0" bw="1" slack="50"/>
<pin id="499" dir="1" index="1" bw="1" slack="2147483647"/>
</pin_list>
<bind>
<opset="or_cond "/>
</bind>
</comp>

<comp id="501" class="1005" name="j_reg_501">
<pin_list>
<pin id="502" dir="0" index="0" bw="5" slack="0"/>
<pin id="503" dir="1" index="1" bw="5" slack="0"/>
</pin_list>
<bind>
<opset="j "/>
</bind>
</comp>

<comp id="506" class="1005" name="crop_0_0_load_reg_506">
<pin_list>
<pin id="507" dir="0" index="0" bw="32" slack="1"/>
<pin id="508" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="crop_0_0_load "/>
</bind>
</comp>

<comp id="511" class="1005" name="crop_1_0_load_reg_511">
<pin_list>
<pin id="512" dir="0" index="0" bw="32" slack="19"/>
<pin id="513" dir="1" index="1" bw="32" slack="19"/>
</pin_list>
<bind>
<opset="crop_1_0_load "/>
</bind>
</comp>

<comp id="516" class="1005" name="crop_2_0_load_reg_516">
<pin_list>
<pin id="517" dir="0" index="0" bw="32" slack="30"/>
<pin id="518" dir="1" index="1" bw="32" slack="30"/>
</pin_list>
<bind>
<opset="crop_2_0_load "/>
</bind>
</comp>

<comp id="521" class="1005" name="crop_0_1_load_reg_521">
<pin_list>
<pin id="522" dir="0" index="0" bw="32" slack="9"/>
<pin id="523" dir="1" index="1" bw="32" slack="9"/>
</pin_list>
<bind>
<opset="crop_0_1_load "/>
</bind>
</comp>

<comp id="526" class="1005" name="crop_1_1_load_reg_526">
<pin_list>
<pin id="527" dir="0" index="0" bw="32" slack="20"/>
<pin id="528" dir="1" index="1" bw="32" slack="20"/>
</pin_list>
<bind>
<opset="crop_1_1_load "/>
</bind>
</comp>

<comp id="531" class="1005" name="crop_2_1_load_reg_531">
<pin_list>
<pin id="532" dir="0" index="0" bw="32" slack="39"/>
<pin id="533" dir="1" index="1" bw="32" slack="39"/>
</pin_list>
<bind>
<opset="crop_2_1_load "/>
</bind>
</comp>

<comp id="536" class="1005" name="tmp_5_reg_536">
<pin_list>
<pin id="537" dir="0" index="0" bw="32" slack="40"/>
<pin id="538" dir="1" index="1" bw="32" slack="40"/>
</pin_list>
<bind>
<opset="tmp_5 "/>
</bind>
</comp>

<comp id="541" class="1005" name="crop_0_2_reg_541">
<pin_list>
<pin id="542" dir="0" index="0" bw="32" slack="10"/>
<pin id="543" dir="1" index="1" bw="32" slack="10"/>
</pin_list>
<bind>
<opset="crop_0_2 "/>
</bind>
</comp>

<comp id="546" class="1005" name="crop_1_2_reg_546">
<pin_list>
<pin id="547" dir="0" index="0" bw="32" slack="29"/>
<pin id="548" dir="1" index="1" bw="32" slack="29"/>
</pin_list>
<bind>
<opset="crop_1_2 "/>
</bind>
</comp>

<comp id="551" class="1005" name="tmp_4_0_i_reg_551">
<pin_list>
<pin id="552" dir="0" index="0" bw="32" slack="1"/>
<pin id="553" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_4_0_i "/>
</bind>
</comp>

<comp id="556" class="1005" name="result_2_0_i_reg_556">
<pin_list>
<pin id="557" dir="0" index="0" bw="32" slack="1"/>
<pin id="558" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_0_i "/>
</bind>
</comp>

<comp id="561" class="1005" name="result_2_0_1_i_reg_561">
<pin_list>
<pin id="562" dir="0" index="0" bw="32" slack="1"/>
<pin id="563" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_0_1_i "/>
</bind>
</comp>

<comp id="566" class="1005" name="tmp_4_0_2_i_reg_566">
<pin_list>
<pin id="567" dir="0" index="0" bw="32" slack="1"/>
<pin id="568" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_4_0_2_i "/>
</bind>
</comp>

<comp id="571" class="1005" name="result_2_0_2_i_reg_571">
<pin_list>
<pin id="572" dir="0" index="0" bw="32" slack="1"/>
<pin id="573" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_0_2_i "/>
</bind>
</comp>

<comp id="576" class="1005" name="result_2_1_i_reg_576">
<pin_list>
<pin id="577" dir="0" index="0" bw="32" slack="1"/>
<pin id="578" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_1_i "/>
</bind>
</comp>

<comp id="581" class="1005" name="tmp_4_1_1_i_reg_581">
<pin_list>
<pin id="582" dir="0" index="0" bw="32" slack="1"/>
<pin id="583" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_4_1_1_i "/>
</bind>
</comp>

<comp id="586" class="1005" name="result_2_1_1_i_reg_586">
<pin_list>
<pin id="587" dir="0" index="0" bw="32" slack="1"/>
<pin id="588" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_1_1_i "/>
</bind>
</comp>

<comp id="591" class="1005" name="result_2_1_2_i_reg_591">
<pin_list>
<pin id="592" dir="0" index="0" bw="32" slack="1"/>
<pin id="593" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_1_2_i "/>
</bind>
</comp>

<comp id="596" class="1005" name="tmp_4_2_i_reg_596">
<pin_list>
<pin id="597" dir="0" index="0" bw="32" slack="1"/>
<pin id="598" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_4_2_i "/>
</bind>
</comp>

<comp id="601" class="1005" name="result_2_2_i_reg_601">
<pin_list>
<pin id="602" dir="0" index="0" bw="32" slack="1"/>
<pin id="603" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_2_i "/>
</bind>
</comp>

<comp id="606" class="1005" name="result_2_2_1_i_reg_606">
<pin_list>
<pin id="607" dir="0" index="0" bw="32" slack="1"/>
<pin id="608" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_2_1_i "/>
</bind>
</comp>

<comp id="611" class="1005" name="tmp_4_2_2_i_reg_611">
<pin_list>
<pin id="612" dir="0" index="0" bw="32" slack="1"/>
<pin id="613" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_4_2_2_i "/>
</bind>
</comp>

<comp id="616" class="1005" name="tmp_4_reg_616">
<pin_list>
<pin id="617" dir="0" index="0" bw="32" slack="1"/>
<pin id="618" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_4 "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="93"><net_src comp="4" pin="0"/><net_sink comp="90" pin=0"/></net>

<net id="97"><net_src comp="4" pin="0"/><net_sink comp="94" pin=0"/></net>

<net id="101"><net_src comp="4" pin="0"/><net_sink comp="98" pin=0"/></net>

<net id="105"><net_src comp="4" pin="0"/><net_sink comp="102" pin=0"/></net>

<net id="109"><net_src comp="4" pin="0"/><net_sink comp="106" pin=0"/></net>

<net id="113"><net_src comp="4" pin="0"/><net_sink comp="110" pin=0"/></net>

<net id="117"><net_src comp="40" pin="0"/><net_sink comp="114" pin=0"/></net>

<net id="121"><net_src comp="40" pin="0"/><net_sink comp="118" pin=0"/></net>

<net id="126"><net_src comp="62" pin="0"/><net_sink comp="122" pin=0"/></net>

<net id="127"><net_src comp="0" pin="0"/><net_sink comp="122" pin=1"/></net>

<net id="133"><net_src comp="86" pin="0"/><net_sink comp="128" pin=0"/></net>

<net id="134"><net_src comp="2" pin="0"/><net_sink comp="128" pin=1"/></net>

<net id="140"><net_src comp="60" pin="0"/><net_sink comp="135" pin=1"/></net>

<net id="145"><net_src comp="135" pin="3"/><net_sink comp="141" pin=0"/></net>

<net id="151"><net_src comp="60" pin="0"/><net_sink comp="146" pin=1"/></net>

<net id="156"><net_src comp="146" pin="3"/><net_sink comp="152" pin=0"/></net>

<net id="160"><net_src comp="152" pin="2"/><net_sink comp="141" pin=4"/></net>

<net id="164"><net_src comp="122" pin="2"/><net_sink comp="152" pin=4"/></net>

<net id="168"><net_src comp="42" pin="0"/><net_sink comp="165" pin=0"/></net>

<net id="175"><net_src comp="165" pin="1"/><net_sink comp="169" pin=0"/></net>

<net id="179"><net_src comp="44" pin="0"/><net_sink comp="176" pin=0"/></net>

<net id="186"><net_src comp="176" pin="1"/><net_sink comp="180" pin=0"/></net>

<net id="190"><net_src comp="44" pin="0"/><net_sink comp="187" pin=0"/></net>

<net id="197"><net_src comp="187" pin="1"/><net_sink comp="191" pin=0"/></net>

<net id="202"><net_src comp="64" pin="0"/><net_sink comp="198" pin=1"/></net>

<net id="239"><net_src comp="64" pin="0"/><net_sink comp="235" pin=1"/></net>

<net id="244"><net_src comp="64" pin="0"/><net_sink comp="240" pin=1"/></net>

<net id="249"><net_src comp="66" pin="0"/><net_sink comp="245" pin=1"/></net>

<net id="254"><net_src comp="64" pin="0"/><net_sink comp="250" pin=1"/></net>

<net id="259"><net_src comp="64" pin="0"/><net_sink comp="255" pin=1"/></net>

<net id="264"><net_src comp="169" pin="4"/><net_sink comp="260" pin=0"/></net>

<net id="265"><net_src comp="46" pin="0"/><net_sink comp="260" pin=1"/></net>

<net id="270"><net_src comp="169" pin="4"/><net_sink comp="266" pin=0"/></net>

<net id="271"><net_src comp="48" pin="0"/><net_sink comp="266" pin=1"/></net>

<net id="276"><net_src comp="191" pin="4"/><net_sink comp="272" pin=0"/></net>

<net id="277"><net_src comp="50" pin="0"/><net_sink comp="272" pin=1"/></net>

<net id="283"><net_src comp="272" pin="2"/><net_sink comp="278" pin=0"/></net>

<net id="284"><net_src comp="44" pin="0"/><net_sink comp="278" pin=1"/></net>

<net id="285"><net_src comp="191" pin="4"/><net_sink comp="278" pin=2"/></net>

<net id="290"><net_src comp="180" pin="4"/><net_sink comp="286" pin=0"/></net>

<net id="291"><net_src comp="52" pin="0"/><net_sink comp="286" pin=1"/></net>

<net id="298"><net_src comp="54" pin="0"/><net_sink comp="292" pin=0"/></net>

<net id="299"><net_src comp="286" pin="2"/><net_sink comp="292" pin=1"/></net>

<net id="300"><net_src comp="4" pin="0"/><net_sink comp="292" pin=2"/></net>

<net id="301"><net_src comp="56" pin="0"/><net_sink comp="292" pin=3"/></net>

<net id="306"><net_src comp="292" pin="4"/><net_sink comp="302" pin=0"/></net>

<net id="307"><net_src comp="58" pin="0"/><net_sink comp="302" pin=1"/></net>

<net id="314"><net_src comp="54" pin="0"/><net_sink comp="308" pin=0"/></net>

<net id="315"><net_src comp="180" pin="4"/><net_sink comp="308" pin=1"/></net>

<net id="316"><net_src comp="4" pin="0"/><net_sink comp="308" pin=2"/></net>

<net id="317"><net_src comp="56" pin="0"/><net_sink comp="308" pin=3"/></net>

<net id="322"><net_src comp="308" pin="4"/><net_sink comp="318" pin=0"/></net>

<net id="323"><net_src comp="58" pin="0"/><net_sink comp="318" pin=1"/></net>

<net id="329"><net_src comp="272" pin="2"/><net_sink comp="324" pin=0"/></net>

<net id="330"><net_src comp="302" pin="2"/><net_sink comp="324" pin=1"/></net>

<net id="331"><net_src comp="318" pin="2"/><net_sink comp="324" pin=2"/></net>

<net id="337"><net_src comp="272" pin="2"/><net_sink comp="332" pin=0"/></net>

<net id="338"><net_src comp="286" pin="2"/><net_sink comp="332" pin=1"/></net>

<net id="339"><net_src comp="180" pin="4"/><net_sink comp="332" pin=2"/></net>

<net id="343"><net_src comp="278" pin="3"/><net_sink comp="340" pin=0"/></net>

<net id="344"><net_src comp="340" pin="1"/><net_sink comp="135" pin=2"/></net>

<net id="345"><net_src comp="340" pin="1"/><net_sink comp="146" pin=2"/></net>

<net id="352"><net_src comp="54" pin="0"/><net_sink comp="346" pin=0"/></net>

<net id="353"><net_src comp="278" pin="3"/><net_sink comp="346" pin=1"/></net>

<net id="354"><net_src comp="4" pin="0"/><net_sink comp="346" pin=2"/></net>

<net id="355"><net_src comp="56" pin="0"/><net_sink comp="346" pin=3"/></net>

<net id="360"><net_src comp="346" pin="4"/><net_sink comp="356" pin=0"/></net>

<net id="361"><net_src comp="58" pin="0"/><net_sink comp="356" pin=1"/></net>

<net id="366"><net_src comp="324" pin="3"/><net_sink comp="362" pin=0"/></net>

<net id="367"><net_src comp="356" pin="2"/><net_sink comp="362" pin=1"/></net>

<net id="372"><net_src comp="278" pin="3"/><net_sink comp="368" pin=0"/></net>

<net id="373"><net_src comp="52" pin="0"/><net_sink comp="368" pin=1"/></net>

<net id="377"><net_src comp="374" pin="1"/><net_sink comp="235" pin=0"/></net>

<net id="397"><net_src comp="390" pin="1"/><net_sink comp="393" pin=0"/></net>

<net id="402"><net_src comp="384" pin="1"/><net_sink comp="398" pin=0"/></net>

<net id="407"><net_src comp="378" pin="1"/><net_sink comp="403" pin=0"/></net>

<net id="421"><net_src comp="122" pin="2"/><net_sink comp="417" pin=0"/></net>

<net id="426"><net_src comp="152" pin="2"/><net_sink comp="422" pin=0"/></net>

<net id="431"><net_src comp="141" pin="2"/><net_sink comp="427" pin=0"/></net>

<net id="435"><net_src comp="90" pin="1"/><net_sink comp="432" pin=0"/></net>

<net id="436"><net_src comp="432" pin="1"/><net_sink comp="374" pin=0"/></net>

<net id="437"><net_src comp="432" pin="1"/><net_sink comp="403" pin=1"/></net>

<net id="441"><net_src comp="94" pin="1"/><net_sink comp="438" pin=0"/></net>

<net id="442"><net_src comp="438" pin="1"/><net_sink comp="378" pin=0"/></net>

<net id="443"><net_src comp="438" pin="1"/><net_sink comp="408" pin=0"/></net>

<net id="444"><net_src comp="438" pin="1"/><net_sink comp="427" pin=1"/></net>

<net id="448"><net_src comp="98" pin="1"/><net_sink comp="445" pin=0"/></net>

<net id="449"><net_src comp="445" pin="1"/><net_sink comp="381" pin=0"/></net>

<net id="450"><net_src comp="445" pin="1"/><net_sink comp="398" pin=1"/></net>

<net id="454"><net_src comp="102" pin="1"/><net_sink comp="451" pin=0"/></net>

<net id="455"><net_src comp="451" pin="1"/><net_sink comp="384" pin=0"/></net>

<net id="456"><net_src comp="451" pin="1"/><net_sink comp="411" pin=0"/></net>

<net id="457"><net_src comp="451" pin="1"/><net_sink comp="422" pin=1"/></net>

<net id="461"><net_src comp="106" pin="1"/><net_sink comp="458" pin=0"/></net>

<net id="462"><net_src comp="458" pin="1"/><net_sink comp="387" pin=0"/></net>

<net id="463"><net_src comp="458" pin="1"/><net_sink comp="393" pin=1"/></net>

<net id="467"><net_src comp="110" pin="1"/><net_sink comp="464" pin=0"/></net>

<net id="468"><net_src comp="464" pin="1"/><net_sink comp="390" pin=0"/></net>

<net id="469"><net_src comp="464" pin="1"/><net_sink comp="414" pin=0"/></net>

<net id="470"><net_src comp="464" pin="1"/><net_sink comp="417" pin=1"/></net>

<net id="474"><net_src comp="260" pin="2"/><net_sink comp="471" pin=0"/></net>

<net id="478"><net_src comp="266" pin="2"/><net_sink comp="475" pin=0"/></net>

<net id="479"><net_src comp="475" pin="1"/><net_sink comp="169" pin=2"/></net>

<net id="483"><net_src comp="332" pin="3"/><net_sink comp="480" pin=0"/></net>

<net id="484"><net_src comp="480" pin="1"/><net_sink comp="180" pin=2"/></net>

<net id="488"><net_src comp="135" pin="3"/><net_sink comp="485" pin=0"/></net>

<net id="489"><net_src comp="485" pin="1"/><net_sink comp="141" pin=0"/></net>

<net id="490"><net_src comp="485" pin="1"/><net_sink comp="141" pin=3"/></net>

<net id="494"><net_src comp="146" pin="3"/><net_sink comp="491" pin=0"/></net>

<net id="495"><net_src comp="491" pin="1"/><net_sink comp="152" pin=0"/></net>

<net id="496"><net_src comp="491" pin="1"/><net_sink comp="152" pin=3"/></net>

<net id="500"><net_src comp="362" pin="2"/><net_sink comp="497" pin=0"/></net>

<net id="504"><net_src comp="368" pin="2"/><net_sink comp="501" pin=0"/></net>

<net id="505"><net_src comp="501" pin="1"/><net_sink comp="191" pin=2"/></net>

<net id="509"><net_src comp="374" pin="1"/><net_sink comp="506" pin=0"/></net>

<net id="510"><net_src comp="506" pin="1"/><net_sink comp="235" pin=0"/></net>

<net id="514"><net_src comp="381" pin="1"/><net_sink comp="511" pin=0"/></net>

<net id="515"><net_src comp="511" pin="1"/><net_sink comp="211" pin=1"/></net>

<net id="519"><net_src comp="387" pin="1"/><net_sink comp="516" pin=0"/></net>

<net id="520"><net_src comp="516" pin="1"/><net_sink comp="250" pin=0"/></net>

<net id="524"><net_src comp="408" pin="1"/><net_sink comp="521" pin=0"/></net>

<net id="525"><net_src comp="521" pin="1"/><net_sink comp="203" pin=1"/></net>

<net id="529"><net_src comp="411" pin="1"/><net_sink comp="526" pin=0"/></net>

<net id="530"><net_src comp="526" pin="1"/><net_sink comp="245" pin=0"/></net>

<net id="534"><net_src comp="414" pin="1"/><net_sink comp="531" pin=0"/></net>

<net id="535"><net_src comp="531" pin="1"/><net_sink comp="227" pin=1"/></net>

<net id="539"><net_src comp="122" pin="2"/><net_sink comp="536" pin=0"/></net>

<net id="540"><net_src comp="536" pin="1"/><net_sink comp="255" pin=0"/></net>

<net id="544"><net_src comp="141" pin="2"/><net_sink comp="541" pin=0"/></net>

<net id="545"><net_src comp="541" pin="1"/><net_sink comp="240" pin=0"/></net>

<net id="549"><net_src comp="152" pin="2"/><net_sink comp="546" pin=0"/></net>

<net id="550"><net_src comp="546" pin="1"/><net_sink comp="219" pin=1"/></net>

<net id="554"><net_src comp="235" pin="2"/><net_sink comp="551" pin=0"/></net>

<net id="555"><net_src comp="551" pin="1"/><net_sink comp="198" pin=0"/></net>

<net id="559"><net_src comp="198" pin="2"/><net_sink comp="556" pin=0"/></net>

<net id="560"><net_src comp="556" pin="1"/><net_sink comp="203" pin=0"/></net>

<net id="564"><net_src comp="203" pin="2"/><net_sink comp="561" pin=0"/></net>

<net id="565"><net_src comp="561" pin="1"/><net_sink comp="207" pin=0"/></net>

<net id="569"><net_src comp="240" pin="2"/><net_sink comp="566" pin=0"/></net>

<net id="570"><net_src comp="566" pin="1"/><net_sink comp="207" pin=1"/></net>

<net id="574"><net_src comp="207" pin="2"/><net_sink comp="571" pin=0"/></net>

<net id="575"><net_src comp="571" pin="1"/><net_sink comp="211" pin=0"/></net>

<net id="579"><net_src comp="211" pin="2"/><net_sink comp="576" pin=0"/></net>

<net id="580"><net_src comp="576" pin="1"/><net_sink comp="215" pin=0"/></net>

<net id="584"><net_src comp="245" pin="2"/><net_sink comp="581" pin=0"/></net>

<net id="585"><net_src comp="581" pin="1"/><net_sink comp="215" pin=1"/></net>

<net id="589"><net_src comp="215" pin="2"/><net_sink comp="586" pin=0"/></net>

<net id="590"><net_src comp="586" pin="1"/><net_sink comp="219" pin=0"/></net>

<net id="594"><net_src comp="219" pin="2"/><net_sink comp="591" pin=0"/></net>

<net id="595"><net_src comp="591" pin="1"/><net_sink comp="223" pin=0"/></net>

<net id="599"><net_src comp="250" pin="2"/><net_sink comp="596" pin=0"/></net>

<net id="600"><net_src comp="596" pin="1"/><net_sink comp="223" pin=1"/></net>

<net id="604"><net_src comp="223" pin="2"/><net_sink comp="601" pin=0"/></net>

<net id="605"><net_src comp="601" pin="1"/><net_sink comp="227" pin=0"/></net>

<net id="609"><net_src comp="227" pin="2"/><net_sink comp="606" pin=0"/></net>

<net id="610"><net_src comp="606" pin="1"/><net_sink comp="231" pin=0"/></net>

<net id="614"><net_src comp="255" pin="2"/><net_sink comp="611" pin=0"/></net>

<net id="615"><net_src comp="611" pin="1"/><net_sink comp="231" pin=1"/></net>

<net id="619"><net_src comp="231" pin="2"/><net_sink comp="616" pin=0"/></net>

<net id="620"><net_src comp="616" pin="1"/><net_sink comp="128" pin=2"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: out_stream_V | {52 }
 - Input state : 
	Port: convolve : in_stream_V | {3 }
  - Chain level:
	State 1
	State 2
		exitcond_flatten : 1
		indvar_flatten_next : 1
		exitcond : 1
		pos_y_assign_mid2 : 2
		i_s : 1
		tmp : 2
		icmp : 3
		tmp_1 : 1
		icmp1 : 2
		tmp_mid2 : 4
		i_mid2 : 2
		tmp_i : 3
		temp_array_0_assign_1 : 4
		crop_0_2 : 5
		temp_array_1_assign_1 : 4
		crop_1_2 : 5
		tmp_3 : 3
		icmp2 : 4
		or_cond : 5
		StgValue_87 : 5
		j : 3
	State 3
		StgValue_95 : 1
		StgValue_96 : 1
		StgValue_97 : 1
		StgValue_105 : 1
		tmp_4_0_i : 1
		StgValue_109 : 1
		StgValue_110 : 1
	State 4
	State 5
	State 6
	State 7
	State 8
	State 9
	State 10
	State 11
	State 12
	State 13
	State 14
	State 15
	State 16
	State 17
	State 18
	State 19
	State 20
	State 21
	State 22
	State 23
	State 24
	State 25
	State 26
	State 27
	State 28
	State 29
	State 30
	State 31
	State 32
	State 33
	State 34
	State 35
	State 36
	State 37
	State 38
	State 39
	State 40
	State 41
	State 42
	State 43
	State 44
	State 45
	State 46
	State 47
	State 48
	State 49
	State 50
	State 51
	State 52
		empty : 1
	State 53


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|----------------------------|---------|---------|---------|
| Operation|       Functional Unit      |  DSP48E |    FF   |   LUT   |
|----------|----------------------------|---------|---------|---------|
|          |         grp_fu_198         |    2    |   205   |   390   |
|          |         grp_fu_203         |    2    |   205   |   390   |
|          |         grp_fu_207         |    2    |   205   |   390   |
|          |         grp_fu_211         |    2    |   205   |   390   |
|   fadd   |         grp_fu_215         |    2    |   205   |   390   |
|          |         grp_fu_219         |    2    |   205   |   390   |
|          |         grp_fu_223         |    2    |   205   |   390   |
|          |         grp_fu_227         |    2    |   205   |   390   |
|          |         grp_fu_231         |    2    |   205   |   390   |
|----------|----------------------------|---------|---------|---------|
|          |         grp_fu_235         |    3    |   143   |   321   |
|          |         grp_fu_240         |    3    |   143   |   321   |
|   fmul   |         grp_fu_245         |    3    |   143   |   321   |
|          |         grp_fu_250         |    3    |   143   |   321   |
|          |         grp_fu_255         |    3    |   143   |   321   |
|----------|----------------------------|---------|---------|---------|
|          |   exitcond_flatten_fu_260  |    0    |    0    |    13   |
|          |       exitcond_fu_272      |    0    |    0    |    11   |
|   icmp   |         icmp_fu_302        |    0    |    0    |    9    |
|          |        icmp1_fu_318        |    0    |    0    |    9    |
|          |        icmp2_fu_356        |    0    |    0    |    9    |
|----------|----------------------------|---------|---------|---------|
|          | indvar_flatten_next_fu_266 |    0    |    0    |    16   |
|    add   |         i_s_fu_286         |    0    |    0    |    15   |
|          |          j_fu_368          |    0    |    0    |    15   |
|----------|----------------------------|---------|---------|---------|
|          |  pos_y_assign_mid2_fu_278  |    0    |    0    |    5    |
|  select  |       tmp_mid2_fu_324      |    0    |    0    |    2    |
|          |        i_mid2_fu_332       |    0    |    0    |    5    |
|----------|----------------------------|---------|---------|---------|
|    and   |       or_cond_fu_362       |    0    |    0    |    8    |
|----------|----------------------------|---------|---------|---------|
|   read   |      tmp_5_read_fu_122     |    0    |    0    |    0    |
|----------|----------------------------|---------|---------|---------|
|   write  |  StgValue_180_write_fu_128 |    0    |    0    |    0    |
|----------|----------------------------|---------|---------|---------|
|          |         tmp_fu_292         |    0    |    0    |    0    |
|partselect|        tmp_1_fu_308        |    0    |    0    |    0    |
|          |        tmp_3_fu_346        |    0    |    0    |    0    |
|----------|----------------------------|---------|---------|---------|
|   zext   |        tmp_i_fu_340        |    0    |    0    |    0    |
|----------|----------------------------|---------|---------|---------|
|   Total  |                            |    33   |   2560  |   5232  |
|----------|----------------------------|---------|---------|---------|

Memories:
+-------------------+--------+--------+--------+
|                   |  BRAM  |   FF   |   LUT  |
+-------------------+--------+--------+--------+
|temp_array_0_assign|    0   |   64   |   10   |
|temp_array_1_assign|    0   |   64   |   10   |
+-------------------+--------+--------+--------+
|       Total       |    0   |   128  |   20   |
+-------------------+--------+--------+--------+

* Register list:
+-----------------------------+--------+
|                             |   FF   |
+-----------------------------+--------+
|    crop_0_0_load_reg_506    |   32   |
|       crop_0_0_reg_432      |   32   |
|    crop_0_1_load_reg_521    |   32   |
|       crop_0_1_reg_438      |   32   |
|       crop_0_2_reg_541      |   32   |
|    crop_1_0_load_reg_511    |   32   |
|       crop_1_0_reg_445      |   32   |
|    crop_1_1_load_reg_526    |   32   |
|       crop_1_1_reg_451      |   32   |
|       crop_1_2_reg_546      |   32   |
|    crop_2_0_load_reg_516    |   32   |
|       crop_2_0_reg_458      |   32   |
|    crop_2_1_load_reg_531    |   32   |
|       crop_2_1_reg_464      |   32   |
|   exitcond_flatten_reg_471  |    1   |
|        i_mid2_reg_480       |    5   |
|          i_reg_176          |    5   |
| indvar_flatten_next_reg_475 |    9   |
|    indvar_flatten_reg_165   |    9   |
|          j_reg_501          |    5   |
|       or_cond_reg_497       |    1   |
|     pos_y_assign_reg_187    |    5   |
|    result_2_0_1_i_reg_561   |   32   |
|    result_2_0_2_i_reg_571   |   32   |
|     result_2_0_i_reg_556    |   32   |
|    result_2_1_1_i_reg_586   |   32   |
|    result_2_1_2_i_reg_591   |   32   |
|     result_2_1_i_reg_576    |   32   |
|    result_2_2_1_i_reg_606   |   32   |
|     result_2_2_i_reg_601    |   32   |
|temp_array_0_assign_1_reg_485|    5   |
|temp_array_1_assign_1_reg_491|    5   |
|     tmp_4_0_2_i_reg_566     |   32   |
|      tmp_4_0_i_reg_551      |   32   |
|     tmp_4_1_1_i_reg_581     |   32   |
|     tmp_4_2_2_i_reg_611     |   32   |
|      tmp_4_2_i_reg_596      |   32   |
|        tmp_4_reg_616        |   32   |
|        tmp_5_reg_536        |   32   |
+-----------------------------+--------+
|            Total            |   978  |
+-----------------------------+--------+

* Multiplexer (MUX) list: 
|-------------------|------|------|------|--------||---------||---------|
|        Comp       |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|-------------------|------|------|------|--------||---------||---------|
| grp_access_fu_141 |  p0  |   2  |   5  |   10   ||    9    |
| grp_access_fu_152 |  p0  |   2  |   5  |   10   ||    9    |
|     grp_fu_235    |  p0  |   2  |  32  |   64   ||    9    |
|-------------------|------|------|------|--------||---------||---------|
|       Total       |      |      |      |   84   ||  5.307  ||    27   |
|-------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+--------+--------+
|           |  BRAM  | DSP48E |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+--------+--------+
|  Function |    -   |   33   |    -   |  2560  |  5232  |
|   Memory  |    0   |    -   |    -   |   128  |   20   |
|Multiplexer|    -   |    -   |    5   |    -   |   27   |
|  Register |    -   |    -   |    -   |   978  |    -   |
+-----------+--------+--------+--------+--------+--------+
|   Total   |    0   |   33   |    5   |  3666  |  5279  |
+-----------+--------+--------+--------+--------+--------+