================================================================ == Vivado HLS Report for 'conv_stream' ================================================================ * Date: Wed May 30 11:44:02 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: axi_port_only * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+----------+ | Latency | Interval | Pipeline | | min | max | min | max | Type | +-----+-----+-----+-----+----------+ | 465| 465| 452| 452| dataflow | +-----+-----+-----+-----+----------+ + Detail: * Instance: N/A * Loop: N/A ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 1 ResetActiveHigh: 1 IsCombinational: 2 IsDatapathOnly: 0 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 6 * Pipeline : 0 * Dataflow Pipeline: 1 DF-Pipeline-0: Size = 6, States = { 1 2 3 4 5 6 } * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> * FSM state operations: : 4.63ns ST_1 : Operation 7 [1/1] (1.00ns) ---> "%out_array_offset_rea = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %out_array_offset)" ---> Core 10 's_axilite' ST_1 : Operation 8 [1/1] (1.00ns) ---> "%in_array_offset_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %in_array_offset)" ---> Core 10 's_axilite' ST_1 : Operation 9 [1/1] (0.00ns) ---> "%out_array_offset_c = alloca i32, align 4" ---> Core 32 'FIFO' ST_1 : Operation 10 [1/1] (0.00ns) ---> "%in_stream_V = alloca float, align 4" [edge_detection/edge_detection.cpp:74] ---> Core 32 'FIFO' ST_1 : Operation 11 [1/1] (0.00ns) ---> "%out_stream_V = alloca float, align 4" [edge_detection/edge_detection.cpp:76] ---> Core 32 'FIFO' ST_1 : Operation 12 [2/2] (3.63ns) ---> "call fastcc void @read_pixel13(float* %in_stream_V, float* %in_array, i32 %in_array_offset_read, i32 %out_array_offset_rea, i32* %out_array_offset_c)" ---> Core 0 '' : 0.00ns ST_2 : Operation 13 [1/2] (0.00ns) ---> "call fastcc void @read_pixel13(float* %in_stream_V, float* %in_array, i32 %in_array_offset_read, i32 %out_array_offset_rea, i32* %out_array_offset_c)" ---> Core 0 '' : 0.00ns ST_3 : Operation 14 [2/2] (0.00ns) ---> "call fastcc void @convolve(float* %in_stream_V, float* %out_stream_V) nounwind" [edge_detection/edge_detection.cpp:79] ---> Core 0 '' : 0.00ns ST_4 : Operation 15 [1/2] (0.00ns) ---> "call fastcc void @convolve(float* %in_stream_V, float* %out_stream_V) nounwind" [edge_detection/edge_detection.cpp:79] ---> Core 0 '' : 0.00ns ST_5 : Operation 16 [2/2] (0.00ns) ---> "call fastcc void @write_pixel(float* %out_stream_V, float* %out_array, i32* nocapture %out_array_offset_c)" [edge_detection/edge_detection.cpp:80] ---> Core 0 '' : 0.00ns ST_6 : Operation 17 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(float* %out_array), !map !47" ST_6 : Operation 18 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(float* %in_array), !map !53" ST_6 : Operation 19 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecDataflowPipeline(i32 -1, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:70] ST_6 : Operation 20 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @conv_stream_str) nounwind" ST_6 : Operation 21 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecChannel([12 x i8]* @in_stream_OC_V_str, i32 1, [1 x i8]* @p_str36, [1 x i8]* @p_str36, i32 32, i32 32, float* %in_stream_V, float* %in_stream_V) nounwind" ST_6 : Operation 22 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)" ST_6 : Operation 23 [1/1] (0.00ns) ---> "%empty_12 = call i32 (...)* @_ssdm_op_SpecChannel([13 x i8]* @out_stream_OC_V_str, i32 1, [1 x i8]* @p_str43, [1 x i8]* @p_str43, i32 32, i32 32, float* %out_stream_V, float* %out_stream_V) nounwind" ST_6 : Operation 24 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %out_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str44, i32 0, i32 0, [1 x i8]* @p_str45, [1 x i8]* @p_str46, [1 x i8]* @p_str47, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str48, [1 x i8]* @p_str49)" ST_6 : Operation 25 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:71] ST_6 : Operation 26 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_6 : Operation 27 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %in_array_offset, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [1 x i8]* @bundle, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_6 : Operation 28 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %out_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [10 x i8]* @p_str10, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_6 : Operation 29 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %out_array_offset, [10 x i8]* @mode7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [1 x i8]* @bundle8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_6 : Operation 30 [1/1] (0.00ns) ---> "%empty_13 = call i32 (...)* @_ssdm_op_SpecChannel([19 x i8]* @out_array_offset_c_s, i32 1, [1 x i8]* @p_str21, [1 x i8]* @p_str21, i32 2, i32 0, i32* %out_array_offset_c, i32* %out_array_offset_c)" ST_6 : Operation 31 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32* %out_array_offset_c, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str22, i32 0, i32 0, [1 x i8]* @p_str23, [1 x i8]* @p_str24, [1 x i8]* @p_str25, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str26, [1 x i8]* @p_str27)" ST_6 : Operation 32 [1/2] (0.00ns) ---> "call fastcc void @write_pixel(float* %out_stream_V, float* %out_array, i32* nocapture %out_array_offset_c)" [edge_detection/edge_detection.cpp:80] ---> Core 0 '' ST_6 : Operation 33 [1/1] (0.00ns) ---> "ret void" [edge_detection/edge_detection.cpp:81] ============================================================ + Verbose Summary: Timing violations ============================================================ Target clock period: 10ns, clock uncertainty: 1.25ns. : 4.63ns The critical path consists of the following: s_axi read on port 'out_array_offset' [5] (1 ns) 'call' operation to 'read_pixel13' [25] (3.63 ns) : 0ns The critical path consists of the following: : 0ns The critical path consists of the following: : 0ns The critical path consists of the following: : 0ns The critical path consists of the following: : 0ns The critical path consists of the following: ============================================================ + Verbose Summary: Binding ============================================================ N/A * FSMD analyzer results: - Output states: - Input state : - Chain level: State 1 State 2 State 3 State 4 State 5 State 6 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ N/A