================================================================ == Vivado HLS Report for 'conv_stream' ================================================================ * Date: Wed May 30 11:44:03 2018 * Version: 2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017) * Project: edge_detection * Solution: axi_port_only * Product family: zynq * Target device: xc7z020clg484-1 ================================================================ == Performance Estimates ================================================================ + Timing (ns): * Summary: +--------+-------+----------+------------+ | Clock | Target| Estimated| Uncertainty| +--------+-------+----------+------------+ |ap_clk | 10.00| 8.75| 1.25| +--------+-------+----------+------------+ + Latency (clock cycles): * Summary: +-----+-----+-----+-----+----------+ | Latency | Interval | Pipeline | | min | max | min | max | Type | +-----+-----+-----+-----+----------+ | 465| 465| 452| 452| dataflow | +-----+-----+-----+-----+----------+ + Detail: * Instance: +-----------------+--------------+-----+-----+-----+-----+---------+ | | | Latency | Interval | Pipeline| | Instance | Module | min | max | min | max | Type | +-----------------+--------------+-----+-----+-----+-----+---------+ |convolve_U0 |convolve | 451| 451| 451| 451| none | |write_pixel_U0 |write_pixel | 332| 332| 332| 332| none | |read_pixel13_U0 |read_pixel13 | 409| 409| 409| 409| none | +-----------------+--------------+-----+-----+-----+-----+---------+ * Loop: N/A ================================================================ == Utilization Estimates ================================================================ * Summary: +-----------------+---------+-------+--------+-------+ | Name | BRAM_18K| DSP48E| FF | LUT | +-----------------+---------+-------+--------+-------+ |DSP | -| -| -| -| |Expression | -| -| 0| 16| |FIFO | 4| -| 105| 132| |Instance | 4| 33| 5591| 7611| |Memory | -| -| -| -| |Multiplexer | -| -| -| -| |Register | -| -| -| -| +-----------------+---------+-------+--------+-------+ |Total | 8| 33| 5696| 7759| +-----------------+---------+-------+--------+-------+ |Available | 280| 220| 106400| 53200| +-----------------+---------+-------+--------+-------+ |Utilization (%) | 2| 15| 5| 14| +-----------------+---------+-------+--------+-------+ + Detail: * Instance: +-------------------------------+-----------------------------+---------+-------+------+------+ | Instance | Module | BRAM_18K| DSP48E| FF | LUT | +-------------------------------+-----------------------------+---------+-------+------+------+ |conv_stream_AXILiteS_s_axi_U |conv_stream_AXILiteS_s_axi | 0| 0| 112| 168| |conv_stream_in_array_m_axi_U |conv_stream_in_array_m_axi | 2| 0| 512| 580| |conv_stream_out_array_m_axi_U |conv_stream_out_array_m_axi | 2| 0| 512| 580| |convolve_U0 |convolve | 0| 33| 4310| 5833| |read_pixel13_U0 |read_pixel13 | 0| 0| 58| 222| |write_pixel_U0 |write_pixel | 0| 0| 87| 228| +-------------------------------+-----------------------------+---------+-------+------+------+ |Total | | 4| 33| 5591| 7611| +-------------------------------+-----------------------------+---------+-------+------+------+ * DSP48: N/A * Memory: N/A * FIFO: +----------------------+---------+----+----+------+-----+---------+ | Name | BRAM_18K| FF | LUT| Depth| Bits| Size:D*B| +----------------------+---------+----+----+------+-----+---------+ |in_stream_V_U | 2| 50| 44| 32| 32| 1024| |out_array_offset_c_U | 0| 5| 44| 2| 32| 64| |out_stream_V_U | 2| 50| 44| 32| 32| 1024| +----------------------+---------+----+----+------+-----+---------+ |Total | 4| 105| 132| 66| 96| 2112| +----------------------+---------+----+----+------+-----+---------+ * Expression: +------------------------------+----------+-------+---+----+------------+------------+ | Variable Name | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1| +------------------------------+----------+-------+---+----+------------+------------+ |ap_idle | and | 0| 0| 8| 1| 1| |read_pixel13_U0_start_full_n | and | 0| 0| 8| 1| 1| +------------------------------+----------+-------+---+----+------------+------------+ |Total | | 0| 0| 16| 2| 2| +------------------------------+----------+-------+---+----+------------+------------+ * Multiplexer: N/A * Register: N/A ================================================================ == Interface ================================================================ * Summary: +--------------------------+-----+-----+------------+--------------+--------------+ | RTL Ports | Dir | Bits| Protocol | Source Object| C Type | +--------------------------+-----+-----+------------+--------------+--------------+ |s_axi_AXILiteS_AWVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_AWADDR | in | 5| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WDATA | in | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_WSTRB | in | 4| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARVALID | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARREADY | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_ARADDR | in | 5| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RDATA | out | 32| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_RRESP | out | 2| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BVALID | out | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BREADY | in | 1| s_axi | AXILiteS | scalar | |s_axi_AXILiteS_BRESP | out | 2| s_axi | AXILiteS | scalar | |ap_clk | in | 1| ap_ctrl_hs | conv_stream | return value | |ap_rst_n | in | 1| ap_ctrl_hs | conv_stream | return value | |interrupt | out | 1| ap_ctrl_hs | conv_stream | return value | |m_axi_in_array_AWVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_AWREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_AWADDR | out | 32| m_axi | in_array | pointer | |m_axi_in_array_AWID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_AWLEN | out | 8| m_axi | in_array | pointer | |m_axi_in_array_AWSIZE | out | 3| m_axi | in_array | pointer | |m_axi_in_array_AWBURST | out | 2| m_axi | in_array | pointer | |m_axi_in_array_AWLOCK | out | 2| m_axi | in_array | pointer | |m_axi_in_array_AWCACHE | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWPROT | out | 3| m_axi | in_array | pointer | |m_axi_in_array_AWQOS | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWREGION | out | 4| m_axi | in_array | pointer | |m_axi_in_array_AWUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_WDATA | out | 32| m_axi | in_array | pointer | |m_axi_in_array_WSTRB | out | 4| m_axi | in_array | pointer | |m_axi_in_array_WLAST | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_WUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARVALID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARREADY | in | 1| m_axi | in_array | pointer | |m_axi_in_array_ARADDR | out | 32| m_axi | in_array | pointer | |m_axi_in_array_ARID | out | 1| m_axi | in_array | pointer | |m_axi_in_array_ARLEN | out | 8| m_axi | in_array | pointer | |m_axi_in_array_ARSIZE | out | 3| m_axi | in_array | pointer | |m_axi_in_array_ARBURST | out | 2| m_axi | in_array | pointer | |m_axi_in_array_ARLOCK | out | 2| m_axi | in_array | pointer | |m_axi_in_array_ARCACHE | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARPROT | out | 3| m_axi | in_array | pointer | |m_axi_in_array_ARQOS | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARREGION | out | 4| m_axi | in_array | pointer | |m_axi_in_array_ARUSER | out | 1| m_axi | in_array | pointer | |m_axi_in_array_RVALID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RREADY | out | 1| m_axi | in_array | pointer | |m_axi_in_array_RDATA | in | 32| m_axi | in_array | pointer | |m_axi_in_array_RLAST | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RUSER | in | 1| m_axi | in_array | pointer | |m_axi_in_array_RRESP | in | 2| m_axi | in_array | pointer | |m_axi_in_array_BVALID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_BREADY | out | 1| m_axi | in_array | pointer | |m_axi_in_array_BRESP | in | 2| m_axi | in_array | pointer | |m_axi_in_array_BID | in | 1| m_axi | in_array | pointer | |m_axi_in_array_BUSER | in | 1| m_axi | in_array | pointer | |m_axi_out_array_AWVALID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_AWREADY | in | 1| m_axi | out_array | pointer | |m_axi_out_array_AWADDR | out | 32| m_axi | out_array | pointer | |m_axi_out_array_AWID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_AWLEN | out | 8| m_axi | out_array | pointer | |m_axi_out_array_AWSIZE | out | 3| m_axi | out_array | pointer | |m_axi_out_array_AWBURST | out | 2| m_axi | out_array | pointer | |m_axi_out_array_AWLOCK | out | 2| m_axi | out_array | pointer | |m_axi_out_array_AWCACHE | out | 4| m_axi | out_array | pointer | |m_axi_out_array_AWPROT | out | 3| m_axi | out_array | pointer | |m_axi_out_array_AWQOS | out | 4| m_axi | out_array | pointer | |m_axi_out_array_AWREGION | out | 4| m_axi | out_array | pointer | |m_axi_out_array_AWUSER | out | 1| m_axi | out_array | pointer | |m_axi_out_array_WVALID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_WREADY | in | 1| m_axi | out_array | pointer | |m_axi_out_array_WDATA | out | 32| m_axi | out_array | pointer | |m_axi_out_array_WSTRB | out | 4| m_axi | out_array | pointer | |m_axi_out_array_WLAST | out | 1| m_axi | out_array | pointer | |m_axi_out_array_WID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_WUSER | out | 1| m_axi | out_array | pointer | |m_axi_out_array_ARVALID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_ARREADY | in | 1| m_axi | out_array | pointer | |m_axi_out_array_ARADDR | out | 32| m_axi | out_array | pointer | |m_axi_out_array_ARID | out | 1| m_axi | out_array | pointer | |m_axi_out_array_ARLEN | out | 8| m_axi | out_array | pointer | |m_axi_out_array_ARSIZE | out | 3| m_axi | out_array | pointer | |m_axi_out_array_ARBURST | out | 2| m_axi | out_array | pointer | |m_axi_out_array_ARLOCK | out | 2| m_axi | out_array | pointer | |m_axi_out_array_ARCACHE | out | 4| m_axi | out_array | pointer | |m_axi_out_array_ARPROT | out | 3| m_axi | out_array | pointer | |m_axi_out_array_ARQOS | out | 4| m_axi | out_array | pointer | |m_axi_out_array_ARREGION | out | 4| m_axi | out_array | pointer | |m_axi_out_array_ARUSER | out | 1| m_axi | out_array | pointer | |m_axi_out_array_RVALID | in | 1| m_axi | out_array | pointer | |m_axi_out_array_RREADY | out | 1| m_axi | out_array | pointer | |m_axi_out_array_RDATA | in | 32| m_axi | out_array | pointer | |m_axi_out_array_RLAST | in | 1| m_axi | out_array | pointer | |m_axi_out_array_RID | in | 1| m_axi | out_array | pointer | |m_axi_out_array_RUSER | in | 1| m_axi | out_array | pointer | |m_axi_out_array_RRESP | in | 2| m_axi | out_array | pointer | |m_axi_out_array_BVALID | in | 1| m_axi | out_array | pointer | |m_axi_out_array_BREADY | out | 1| m_axi | out_array | pointer | |m_axi_out_array_BRESP | in | 2| m_axi | out_array | pointer | |m_axi_out_array_BID | in | 1| m_axi | out_array | pointer | |m_axi_out_array_BUSER | in | 1| m_axi | out_array | pointer | +--------------------------+-----+-----+------------+--------------+--------------+ ============================================================ + Verbose Summary: Synthesis Manager ============================================================ InlineROM: 1 ExposeGlobal: 0 ============================================================ + Verbose Summary: CDFG Model ============================================================ IsTopModel: 1 ResetActiveHigh: 1 IsCombinational: 2 IsDatapathOnly: 2 HasWiredReturn: 1 HasMFsm: 0 HasVarLatency: 1 IsPipeline: 0 IsRtlPipelined: 0 IsInstanceOverlapped: 0 IsDontTouch: 0 HasImplIP: 0 IsGatedGlobalClock: 0 ============================================================ + Verbose Summary: Schedule ============================================================ * Number of FSM states : 6 * Pipeline : 0 * Dataflow Pipeline: 1 DF-Pipeline-0: Size = 6, States = { 1 2 3 4 5 6 } * FSM state transitions: 1 --> 2 / true 2 --> 3 / true 3 --> 4 / true 4 --> 5 / true 5 --> 6 / true 6 --> * FSM state operations: : 4.63ns ST_1 : Operation 7 [1/1] (1.00ns) ---> "%out_array_offset_rea = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %out_array_offset)" ---> Core 10 's_axilite' ST_1 : Operation 8 [1/1] (1.00ns) ---> "%in_array_offset_read = call i32 @_ssdm_op_Read.s_axilite.i32(i32 %in_array_offset)" ---> Core 10 's_axilite' ST_1 : Operation 9 [1/1] (0.00ns) ---> "%out_array_offset_c = alloca i32, align 4" ---> Core 32 'FIFO' ST_1 : Operation 10 [1/1] (0.00ns) ---> "%in_stream_V = alloca float, align 4" [edge_detection/edge_detection.cpp:74] ---> Core 32 'FIFO' ST_1 : Operation 11 [1/1] (0.00ns) ---> "%out_stream_V = alloca float, align 4" [edge_detection/edge_detection.cpp:76] ---> Core 32 'FIFO' ST_1 : Operation 12 [2/2] (3.63ns) ---> "call fastcc void @read_pixel13(float* %in_stream_V, float* %in_array, i32 %in_array_offset_read, i32 %out_array_offset_rea, i32* %out_array_offset_c)" ---> Core 0 '' : 0.00ns ST_2 : Operation 13 [1/2] (0.00ns) ---> "call fastcc void @read_pixel13(float* %in_stream_V, float* %in_array, i32 %in_array_offset_read, i32 %out_array_offset_rea, i32* %out_array_offset_c)" ---> Core 0 '' : 0.00ns ST_3 : Operation 14 [2/2] (0.00ns) ---> "call fastcc void @convolve(float* %in_stream_V, float* %out_stream_V) nounwind" [edge_detection/edge_detection.cpp:79] ---> Core 0 '' : 0.00ns ST_4 : Operation 15 [1/2] (0.00ns) ---> "call fastcc void @convolve(float* %in_stream_V, float* %out_stream_V) nounwind" [edge_detection/edge_detection.cpp:79] ---> Core 0 '' : 0.00ns ST_5 : Operation 16 [2/2] (0.00ns) ---> "call fastcc void @write_pixel(float* %out_stream_V, float* %out_array, i32* nocapture %out_array_offset_c)" [edge_detection/edge_detection.cpp:80] ---> Core 0 '' : 0.00ns ST_6 : Operation 17 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(float* %out_array), !map !47" ST_6 : Operation 18 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecBitsMap(float* %in_array), !map !53" ST_6 : Operation 19 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecDataflowPipeline(i32 -1, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:70] ST_6 : Operation 20 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecTopModule([12 x i8]* @conv_stream_str) nounwind" ST_6 : Operation 21 [1/1] (0.00ns) ---> "%empty = call i32 (...)* @_ssdm_op_SpecChannel([12 x i8]* @in_stream_OC_V_str, i32 1, [1 x i8]* @p_str36, [1 x i8]* @p_str36, i32 32, i32 32, float* %in_stream_V, float* %in_stream_V) nounwind" ST_6 : Operation 22 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str37, i32 0, i32 0, [1 x i8]* @p_str38, [1 x i8]* @p_str39, [1 x i8]* @p_str40, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str41, [1 x i8]* @p_str42)" ST_6 : Operation 23 [1/1] (0.00ns) ---> "%empty_12 = call i32 (...)* @_ssdm_op_SpecChannel([13 x i8]* @out_stream_OC_V_str, i32 1, [1 x i8]* @p_str43, [1 x i8]* @p_str43, i32 32, i32 32, float* %out_stream_V, float* %out_stream_V) nounwind" ST_6 : Operation 24 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %out_stream_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str44, i32 0, i32 0, [1 x i8]* @p_str45, [1 x i8]* @p_str46, [1 x i8]* @p_str47, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str48, [1 x i8]* @p_str49)" ST_6 : Operation 25 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind" [edge_detection/edge_detection.cpp:71] ST_6 : Operation 26 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %in_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [9 x i8]* @p_str8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_6 : Operation 27 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %in_array_offset, [10 x i8]* @mode, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [1 x i8]* @bundle, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_6 : Operation 28 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(float* %out_array, [6 x i8]* @p_str7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [10 x i8]* @p_str10, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_6 : Operation 29 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32 %out_array_offset, [10 x i8]* @mode7, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 400, [1 x i8]* @bundle8, [6 x i8]* @p_str9, [1 x i8]* @p_str1, i32 16, i32 16, i32 16, i32 16, [1 x i8]* @p_str1, [1 x i8]* @p_str1)" ST_6 : Operation 30 [1/1] (0.00ns) ---> "%empty_13 = call i32 (...)* @_ssdm_op_SpecChannel([19 x i8]* @out_array_offset_c_s, i32 1, [1 x i8]* @p_str21, [1 x i8]* @p_str21, i32 2, i32 0, i32* %out_array_offset_c, i32* %out_array_offset_c)" ST_6 : Operation 31 [1/1] (0.00ns) ---> "call void (...)* @_ssdm_op_SpecInterface(i32* %out_array_offset_c, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str22, i32 0, i32 0, [1 x i8]* @p_str23, [1 x i8]* @p_str24, [1 x i8]* @p_str25, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str26, [1 x i8]* @p_str27)" ST_6 : Operation 32 [1/2] (0.00ns) ---> "call fastcc void @write_pixel(float* %out_stream_V, float* %out_array, i32* nocapture %out_array_offset_c)" [edge_detection/edge_detection.cpp:80] ---> Core 0 '' ST_6 : Operation 33 [1/1] (0.00ns) ---> "ret void" [edge_detection/edge_detection.cpp:81] ============================================================ + Verbose Summary: Binding ============================================================ STG Binding: ---------------- STG Properties BEGIN ---------------- - Is combinational: 0 - Is one-state seq: 0 - Is datapath-only: 0 - Is pipelined: 0 - Is top level: 1 Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0 Port [ in_array]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0 Port [ out_array]: wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=1; type=4; pingpong=0; private_global=0; IO mode=m_axi:ce=0 Port [ in_array_offset]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 Port [ out_array_offset]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=0; pingpong=0; private_global=0; IO mode=ap_none:ce=0 ---------------- STG Properties END ------------------ ---------------- Datapath Model BEGIN ---------------- out_array_offset_rea (read ) [ 0010000] in_array_offset_read (read ) [ 0010000] out_array_offset_c (alloca ) [ 0111111] in_stream_V (alloca ) [ 0111111] out_stream_V (alloca ) [ 0011111] StgValue_13 (call ) [ 0000000] StgValue_15 (call ) [ 0000000] StgValue_17 (specbitsmap ) [ 0000000] StgValue_18 (specbitsmap ) [ 0000000] StgValue_19 (specdataflowpipeline) [ 0000000] StgValue_20 (spectopmodule ) [ 0000000] empty (specchannel ) [ 0000000] StgValue_22 (specinterface ) [ 0000000] empty_12 (specchannel ) [ 0000000] StgValue_24 (specinterface ) [ 0000000] StgValue_25 (specinterface ) [ 0000000] StgValue_26 (specinterface ) [ 0000000] StgValue_27 (specinterface ) [ 0000000] StgValue_28 (specinterface ) [ 0000000] StgValue_29 (specinterface ) [ 0000000] empty_13 (specchannel ) [ 0000000] StgValue_31 (specinterface ) [ 0000000] StgValue_32 (call ) [ 0000000] StgValue_33 (ret ) [ 0000000] ---------------- Datapath Model END ------------------ * FSMD analyzer results: - Output states: Port: out_array | {5 6 } - Input state : Port: conv_stream : in_array | {1 2 } Port: conv_stream : in_array_offset | {1 } Port: conv_stream : out_array_offset | {1 } - Chain level: State 1 StgValue_12 : 1 State 2 State 3 State 4 State 5 State 6 ============================================================ + Verbose Summary: Datapath Resource usage ============================================================ * Functional unit list: |----------|----------------------------------|---------|---------|---------|---------|---------| | Operation| Functional Unit | BRAM | DSP48E | Delay | FF | LUT | |----------|----------------------------------|---------|---------|---------|---------|---------| | | grp_convolve_fu_138 | 0 | 33 | 5.307 | 3666 | 5279 | | call | grp_write_pixel_fu_144 | 0 | 0 | 3.538 | 113 | 38 | | | grp_read_pixel13_fu_152 | 0 | 0 | 1.769 | 83 | 38 | |----------|----------------------------------|---------|---------|---------|---------|---------| | read | out_array_offset_rea_read_fu_126 | 0 | 0 | 0 | 0 | 0 | | | in_array_offset_read_read_fu_132 | 0 | 0 | 0 | 0 | 0 | |----------|----------------------------------|---------|---------|---------|---------|---------| | Total | | 0 | 33 | 10.614 | 3862 | 5355 | |----------|----------------------------------|---------|---------|---------|---------|---------| Memories: N/A * Register list: +----------------------------+--------+ | | FF | +----------------------------+--------+ |in_array_offset_read_reg_169| 32 | | in_stream_V_reg_180 | 32 | | out_array_offset_c_reg_174 | 32 | |out_array_offset_rea_reg_164| 32 | | out_stream_V_reg_186 | 32 | +----------------------------+--------+ | Total | 160 | +----------------------------+--------+ * Multiplexer (MUX) list: |-------------------------|------|------|------|--------||---------||---------| | Comp | Pin | Size | BW | S x BW || Delay || LUT | |-------------------------|------|------|------|--------||---------||---------| | grp_read_pixel13_fu_152 | p3 | 2 | 32 | 64 || 9 | | grp_read_pixel13_fu_152 | p4 | 2 | 32 | 64 || 9 | |-------------------------|------|------|------|--------||---------||---------| | Total | | | | 128 || 3.538 || 18 | |-------------------------|------|------|------|--------||---------||---------| * Summary: +-----------+--------+--------+--------+--------+--------+ | | BRAM | DSP48E | Delay | FF | LUT | +-----------+--------+--------+--------+--------+--------+ | Function | 0 | 33 | 10 | 3862 | 5355 | | Memory | - | - | - | - | - | |Multiplexer| - | - | 3 | - | 18 | | Register | - | - | - | 160 | - | +-----------+--------+--------+--------+--------+--------+ | Total | 0 | 33 | 14 | 4022 | 5373 | +-----------+--------+--------+--------+--------+--------+