================================================================
== Vivado HLS Report for 'compute_pixel'
================================================================
* Date:           Tue May 29 19:06:49 2018

* Version:        2017.4 (Build 2086221 on Fri Dec 15 21:13:33 MST 2017)
* Project:        edge_detection
* Solution:       axi_port_only
* Product family: zynq
* Target device:  xc7z020clg484-1


================================================================
== Performance Estimates
================================================================
+ Timing (ns): 
    * Summary: 
    +--------+-------+----------+------------+
    |  Clock | Target| Estimated| Uncertainty|
    +--------+-------+----------+------------+
    |ap_clk  |  10.00|      9.17|        1.25|
    +--------+-------+----------+------------+

+ Latency (clock cycles): 
    * Summary: 
    +-----+-----+-----+-----+----------+
    |  Latency  |  Interval | Pipeline |
    | min | max | min | max |   Type   |
    +-----+-----+-----+-----+----------+
    |   53|   53|    5|    5| function |
    +-----+-----+-----+-----+----------+

    + Detail: 
        * Instance: 
        N/A

        * Loop: 
        N/A



================================================================
== Utilization Estimates
================================================================
* Summary: 
+-----------------+---------+-------+--------+-------+
|       Name      | BRAM_18K| DSP48E|   FF   |  LUT  |
+-----------------+---------+-------+--------+-------+
|DSP              |        -|      -|       -|      -|
|Expression       |        -|      -|       0|     24|
|FIFO             |        -|      -|       -|      -|
|Instance         |        -|      7|     553|   1101|
|Memory           |        -|      -|       -|      -|
|Multiplexer      |        -|      -|       -|    246|
|Register         |        0|      -|     816|    128|
+-----------------+---------+-------+--------+-------+
|Total            |        0|      7|    1369|   1499|
+-----------------+---------+-------+--------+-------+
|Available        |      280|    220|  106400|  53200|
+-----------------+---------+-------+--------+-------+
|Utilization (%)  |        0|      3|       1|      2|
+-----------------+---------+-------+--------+-------+

+ Detail: 
    * Instance: 
    +-------------------------+----------------------+---------+-------+-----+-----+
    |         Instance        |        Module        | BRAM_18K| DSP48E|  FF | LUT |
    +-------------------------+----------------------+---------+-------+-----+-----+
    |conv_stream_fadd_bkb_U6  |conv_stream_fadd_bkb  |        0|      2|  205|  390|
    |conv_stream_fadd_bkb_U7  |conv_stream_fadd_bkb  |        0|      2|  205|  390|
    |conv_stream_fmul_cud_U8  |conv_stream_fmul_cud  |        0|      3|  143|  321|
    +-------------------------+----------------------+---------+-------+-----+-----+
    |Total                    |                      |        0|      7|  553| 1101|
    +-------------------------+----------------------+---------+-------+-----+-----+

    * DSP48: 
    N/A

    * Memory: 
    N/A

    * FIFO: 
    N/A

    * Expression: 
    +-----------------------------+----------+-------+---+----+------------+------------+
    |        Variable Name        | Operation| DSP48E| FF| LUT| Bitwidth P0| Bitwidth P1|
    +-----------------------------+----------+-------+---+----+------------+------------+
    |ap_block_pp0_stage0_11001    |    and   |      0|  0|   8|           1|           1|
    |ap_block_pp0_stage0_subdone  |    or    |      0|  0|   8|           1|           1|
    |ap_enable_pp0                |    xor   |      0|  0|   8|           1|           2|
    +-----------------------------+----------+-------+---+----+------------+------------+
    |Total                        |          |      0|  0|  24|           3|           4|
    +-----------------------------+----------+-------+---+----+------------+------------+

    * Multiplexer: 
    +--------------------------+----+-----------+-----+-----------+
    |           Name           | LUT| Input Size| Bits| Total Bits|
    +--------------------------+----+-----------+-----+-----------+
    |A_address0                |  33|          6|    4|         24|
    |A_address1                |  27|          5|    4|         20|
    |ap_NS_fsm                 |  33|          6|    1|          6|
    |ap_enable_reg_pp0_iter0   |   9|          2|    1|          2|
    |ap_enable_reg_pp0_iter10  |   9|          2|    1|          2|
    |grp_fu_112_p0             |  33|          6|   32|        192|
    |grp_fu_112_p1             |  33|          6|   32|        192|
    |grp_fu_117_p0             |  27|          5|   32|        160|
    |grp_fu_117_p1             |  27|          5|   32|        160|
    |grp_fu_121_p1             |  15|          3|   32|         96|
    +--------------------------+----+-----------+-----+-----------+
    |Total                     | 246|         46|  171|        854|
    +--------------------------+----+-----------+-----+-----------+

    * Register: 
    +-----------------------------+----+----+-----+-----------+
    |             Name            | FF | LUT| Bits| Const Bits|
    +-----------------------------+----+----+-----+-----------+
    |A_load_1_reg_193             |  32|   0|   32|          0|
    |A_load_3_reg_228             |  32|   0|   32|          0|
    |A_load_5_reg_248             |  32|   0|   32|          0|
    |A_load_7_reg_268             |  32|   0|   32|          0|
    |ap_CS_fsm                    |   5|   0|    5|          0|
    |ap_enable_reg_pp0_iter0_reg  |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter1      |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter10     |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter2      |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter3      |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter4      |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter5      |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter6      |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter7      |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter8      |   1|   0|    1|          0|
    |ap_enable_reg_pp0_iter9      |   1|   0|    1|          0|
    |result_2_0_1_reg_218         |  32|   0|   32|          0|
    |result_2_0_2_reg_233         |  32|   0|   32|          0|
    |result_2_1_1_reg_253         |  32|   0|   32|          0|
    |result_2_1_2_reg_258         |  32|   0|   32|          0|
    |result_2_1_reg_238           |  32|   0|   32|          0|
    |result_2_2_1_reg_278         |  32|   0|   32|          0|
    |result_2_2_reg_273           |  32|   0|   32|          0|
    |result_2_reg_213             |  32|   0|   32|          0|
    |tmp_10_0_2_reg_183           |  32|   0|   32|          0|
    |tmp_10_1_1_reg_198           |  32|   0|   32|          0|
    |tmp_10_2_2_reg_208           |  32|   0|   32|          0|
    |tmp_10_2_reg_203             |  32|   0|   32|          0|
    |tmp_s_reg_168                |  32|   0|   32|          0|
    |tmp_10_0_2_reg_183           |  64|  32|   32|          0|
    |tmp_10_1_1_reg_198           |  64|  32|   32|          0|
    |tmp_10_2_2_reg_208           |  64|  32|   32|          0|
    |tmp_10_2_reg_203             |  64|  32|   32|          0|
    +-----------------------------+----+----+-----+-----------+
    |Total                        | 816| 128|  688|          0|
    +-----------------------------+----+----+-----+-----------+



================================================================
== Interface
================================================================
* Summary: 
+------------+-----+-----+------------+---------------+--------------+
|  RTL Ports | Dir | Bits|  Protocol  | Source Object |    C Type    |
+------------+-----+-----+------------+---------------+--------------+
|ap_clk      |  in |    1| ap_ctrl_hs | compute_pixel | return value |
|ap_rst      |  in |    1| ap_ctrl_hs | compute_pixel | return value |
|ap_start    |  in |    1| ap_ctrl_hs | compute_pixel | return value |
|ap_done     | out |    1| ap_ctrl_hs | compute_pixel | return value |
|ap_idle     | out |    1| ap_ctrl_hs | compute_pixel | return value |
|ap_ready    | out |    1| ap_ctrl_hs | compute_pixel | return value |
|ap_ce       |  in |    1| ap_ctrl_hs | compute_pixel | return value |
|ap_return   | out |   32| ap_ctrl_hs | compute_pixel | return value |
|A_address0  | out |    4|  ap_memory |       A       |     array    |
|A_ce0       | out |    1|  ap_memory |       A       |     array    |
|A_q0        |  in |   32|  ap_memory |       A       |     array    |
|A_address1  | out |    4|  ap_memory |       A       |     array    |
|A_ce1       | out |    1|  ap_memory |       A       |     array    |
|A_q1        |  in |   32|  ap_memory |       A       |     array    |
+------------+-----+-----+------------+---------------+--------------+

============================================================
+ Verbose Summary: Synthesis Manager
============================================================
InlineROM: 1
ExposeGlobal: 0
============================================================
+ Verbose Summary: CDFG Model
============================================================
IsTopModel: 0
ResetActiveHigh: 1
IsCombinational: 2
IsDatapathOnly: 2
HasWiredReturn: 1
HasMFsm: 2
HasVarLatency: 0
IsPipeline: 1
IsRtlPipelined: 1
IsInstanceOverlapped: 0
IsDontTouch: 0
HasImplIP: 0
IsGatedGlobalClock: 0

+ Individual pipeline summary: 
  * Pipeline-0: initiation interval (II) = 5, depth = 54


============================================================
+ Verbose Summary: Schedule
============================================================
* Number of FSM states : 54
* Pipeline : 1
  Pipeline-0 : II = 5, D = 54, States = { 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 }
* Dataflow Pipeline: 0

* FSM state transitions: 
1 --> 
	2  / true
2 --> 
	3  / true
3 --> 
	4  / true
4 --> 
	5  / true
5 --> 
	6  / true
6 --> 
	7  / true
7 --> 
	8  / true
8 --> 
	9  / true
9 --> 
	10  / true
10 --> 
	11  / true
11 --> 
	12  / true
12 --> 
	13  / true
13 --> 
	14  / true
14 --> 
	15  / true
15 --> 
	16  / true
16 --> 
	17  / true
17 --> 
	18  / true
18 --> 
	19  / true
19 --> 
	20  / true
20 --> 
	21  / true
21 --> 
	22  / true
22 --> 
	23  / true
23 --> 
	24  / true
24 --> 
	25  / true
25 --> 
	26  / true
26 --> 
	27  / true
27 --> 
	28  / true
28 --> 
	29  / true
29 --> 
	30  / true
30 --> 
	31  / true
31 --> 
	32  / true
32 --> 
	33  / true
33 --> 
	34  / true
34 --> 
	35  / true
35 --> 
	36  / true
36 --> 
	37  / true
37 --> 
	38  / true
38 --> 
	39  / true
39 --> 
	40  / true
40 --> 
	41  / true
41 --> 
	42  / true
42 --> 
	43  / true
43 --> 
	44  / true
44 --> 
	45  / true
45 --> 
	46  / true
46 --> 
	47  / true
47 --> 
	48  / true
48 --> 
	49  / true
49 --> 
	50  / true
50 --> 
	51  / true
51 --> 
	52  / true
52 --> 
	53  / true
53 --> 
	54  / true
54 --> 

* FSM state operations: 

 <State 1> : 2.32ns
ST_1 : Operation 55 [1/1] (0.00ns)   --->   "%A_addr = getelementptr [9 x float]* %A, i64 0, i64 0" [edge_detection/edge_detection.cpp:8]
ST_1 : Operation 56 [2/2] (2.32ns)   --->   "%A_load = load float* %A_addr, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 2> : 9.17ns
ST_2 : Operation 57 [1/1] (0.00ns)   --->   "%A_addr_2 = getelementptr [9 x float]* %A, i64 0, i64 2" [edge_detection/edge_detection.cpp:8]
ST_2 : Operation 58 [1/2] (2.32ns)   --->   "%A_load = load float* %A_addr, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>
ST_2 : Operation 59 [4/4] (6.84ns)   --->   "%tmp_s = fmul float %A_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_2 : Operation 60 [2/2] (2.32ns)   --->   "%A_load_2 = load float* %A_addr_2, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 3> : 9.17ns
ST_3 : Operation 61 [1/1] (0.00ns)   --->   "%A_addr_4 = getelementptr [9 x float]* %A, i64 0, i64 4" [edge_detection/edge_detection.cpp:8]
ST_3 : Operation 62 [3/4] (5.70ns)   --->   "%tmp_s = fmul float %A_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 63 [1/2] (2.32ns)   --->   "%A_load_2 = load float* %A_addr_2, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>
ST_3 : Operation 64 [4/4] (6.84ns)   --->   "%tmp_10_0_2 = fmul float %A_load_2, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_3 : Operation 65 [2/2] (2.32ns)   --->   "%A_load_4 = load float* %A_addr_4, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 4> : 9.17ns
ST_4 : Operation 66 [1/1] (0.00ns)   --->   "%A_addr_6 = getelementptr [9 x float]* %A, i64 0, i64 6" [edge_detection/edge_detection.cpp:8]
ST_4 : Operation 67 [2/4] (5.70ns)   --->   "%tmp_s = fmul float %A_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 68 [3/4] (5.70ns)   --->   "%tmp_10_0_2 = fmul float %A_load_2, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 69 [1/2] (2.32ns)   --->   "%A_load_4 = load float* %A_addr_4, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>
ST_4 : Operation 70 [4/4] (6.84ns)   --->   "%tmp_10_1_1 = fmul float %A_load_4, -4.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_4 : Operation 71 [2/2] (2.32ns)   --->   "%A_load_6 = load float* %A_addr_6, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 5> : 9.17ns
ST_5 : Operation 72 [1/1] (0.00ns)   --->   "%A_addr_8 = getelementptr [9 x float]* %A, i64 0, i64 8" [edge_detection/edge_detection.cpp:8]
ST_5 : Operation 73 [1/4] (5.70ns)   --->   "%tmp_s = fmul float %A_load, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 74 [2/4] (5.70ns)   --->   "%tmp_10_0_2 = fmul float %A_load_2, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 75 [3/4] (5.70ns)   --->   "%tmp_10_1_1 = fmul float %A_load_4, -4.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 76 [1/2] (2.32ns)   --->   "%A_load_6 = load float* %A_addr_6, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>
ST_5 : Operation 77 [4/4] (6.84ns)   --->   "%tmp_10_2 = fmul float %A_load_6, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_5 : Operation 78 [2/2] (2.32ns)   --->   "%A_load_8 = load float* %A_addr_8, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 6> : 9.17ns
ST_6 : Operation 79 [1/1] (0.00ns)   --->   "%A_addr_1 = getelementptr [9 x float]* %A, i64 0, i64 1" [edge_detection/edge_detection.cpp:8]
ST_6 : Operation 80 [5/5] (8.39ns)   --->   "%result_2 = fadd float %tmp_s, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_6 : Operation 81 [2/2] (2.32ns)   --->   "%A_load_1 = load float* %A_addr_1, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>
ST_6 : Operation 82 [1/4] (5.70ns)   --->   "%tmp_10_0_2 = fmul float %A_load_2, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_6 : Operation 83 [2/4] (5.70ns)   --->   "%tmp_10_1_1 = fmul float %A_load_4, -4.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_6 : Operation 84 [3/4] (5.70ns)   --->   "%tmp_10_2 = fmul float %A_load_6, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_6 : Operation 85 [1/2] (2.32ns)   --->   "%A_load_8 = load float* %A_addr_8, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>
ST_6 : Operation 86 [4/4] (6.84ns)   --->   "%tmp_10_2_2 = fmul float %A_load_8, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 7> : 7.26ns
ST_7 : Operation 87 [4/5] (7.25ns)   --->   "%result_2 = fadd float %tmp_s, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_7 : Operation 88 [1/2] (2.32ns)   --->   "%A_load_1 = load float* %A_addr_1, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>
ST_7 : Operation 89 [1/4] (5.70ns)   --->   "%tmp_10_1_1 = fmul float %A_load_4, -4.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_7 : Operation 90 [2/4] (5.70ns)   --->   "%tmp_10_2 = fmul float %A_load_6, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_7 : Operation 91 [3/4] (5.70ns)   --->   "%tmp_10_2_2 = fmul float %A_load_8, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 8> : 7.26ns
ST_8 : Operation 92 [3/5] (7.25ns)   --->   "%result_2 = fadd float %tmp_s, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_8 : Operation 93 [1/4] (5.70ns)   --->   "%tmp_10_2 = fmul float %A_load_6, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>
ST_8 : Operation 94 [2/4] (5.70ns)   --->   "%tmp_10_2_2 = fmul float %A_load_8, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 9> : 7.26ns
ST_9 : Operation 95 [2/5] (7.25ns)   --->   "%result_2 = fadd float %tmp_s, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_9 : Operation 96 [1/4] (5.70ns)   --->   "%tmp_10_2_2 = fmul float %A_load_8, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 100 'FMul' <Latency = 3> <II = 1> <Delay = 5.70> <FuncUnit> <Opcode : 'fmul'> <InPorts = 2> <OutPorts = 1>

 <State 10> : 7.26ns
ST_10 : Operation 97 [1/5] (7.25ns)   --->   "%result_2 = fadd float %tmp_s, 0.000000e+00" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 11> : 7.26ns
ST_11 : Operation 98 [5/5] (7.25ns)   --->   "%result_2_0_1 = fadd float %result_2, %A_load_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 12> : 7.26ns
ST_12 : Operation 99 [4/5] (7.25ns)   --->   "%result_2_0_1 = fadd float %result_2, %A_load_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 13> : 7.26ns
ST_13 : Operation 100 [3/5] (7.25ns)   --->   "%result_2_0_1 = fadd float %result_2, %A_load_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 14> : 7.26ns
ST_14 : Operation 101 [2/5] (7.25ns)   --->   "%result_2_0_1 = fadd float %result_2, %A_load_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 15> : 7.26ns
ST_15 : Operation 102 [1/5] (7.25ns)   --->   "%result_2_0_1 = fadd float %result_2, %A_load_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 16> : 0.00ns

 <State 17> : 8.40ns
ST_17 : Operation 103 [1/1] (0.00ns)   --->   "%A_addr_3 = getelementptr [9 x float]* %A, i64 0, i64 3" [edge_detection/edge_detection.cpp:8]
ST_17 : Operation 104 [5/5] (8.39ns)   --->   "%result_2_0_2 = fadd float %result_2_0_1, %tmp_10_0_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_17 : Operation 105 [2/2] (2.32ns)   --->   "%A_load_3 = load float* %A_addr_3, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 18> : 7.26ns
ST_18 : Operation 106 [4/5] (7.25ns)   --->   "%result_2_0_2 = fadd float %result_2_0_1, %tmp_10_0_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_18 : Operation 107 [1/2] (2.32ns)   --->   "%A_load_3 = load float* %A_addr_3, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 19> : 7.26ns
ST_19 : Operation 108 [3/5] (7.25ns)   --->   "%result_2_0_2 = fadd float %result_2_0_1, %tmp_10_0_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 20> : 7.26ns
ST_20 : Operation 109 [2/5] (7.25ns)   --->   "%result_2_0_2 = fadd float %result_2_0_1, %tmp_10_0_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 21> : 7.26ns
ST_21 : Operation 110 [1/5] (7.25ns)   --->   "%result_2_0_2 = fadd float %result_2_0_1, %tmp_10_0_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 22> : 7.26ns
ST_22 : Operation 111 [5/5] (7.25ns)   --->   "%result_2_1 = fadd float %result_2_0_2, %A_load_3" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 23> : 7.26ns
ST_23 : Operation 112 [4/5] (7.25ns)   --->   "%result_2_1 = fadd float %result_2_0_2, %A_load_3" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 24> : 7.26ns
ST_24 : Operation 113 [3/5] (7.25ns)   --->   "%result_2_1 = fadd float %result_2_0_2, %A_load_3" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 25> : 7.26ns
ST_25 : Operation 114 [2/5] (7.25ns)   --->   "%result_2_1 = fadd float %result_2_0_2, %A_load_3" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 26> : 7.26ns
ST_26 : Operation 115 [1/5] (7.25ns)   --->   "%result_2_1 = fadd float %result_2_0_2, %A_load_3" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 27> : 0.00ns

 <State 28> : 8.40ns
ST_28 : Operation 116 [1/1] (0.00ns)   --->   "%A_addr_5 = getelementptr [9 x float]* %A, i64 0, i64 5" [edge_detection/edge_detection.cpp:8]
ST_28 : Operation 117 [5/5] (8.39ns)   --->   "%result_2_1_1 = fadd float %result_2_1, %tmp_10_1_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_28 : Operation 118 [2/2] (2.32ns)   --->   "%A_load_5 = load float* %A_addr_5, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 29> : 7.26ns
ST_29 : Operation 119 [4/5] (7.25ns)   --->   "%result_2_1_1 = fadd float %result_2_1, %tmp_10_1_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_29 : Operation 120 [1/2] (2.32ns)   --->   "%A_load_5 = load float* %A_addr_5, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 30> : 7.26ns
ST_30 : Operation 121 [3/5] (7.25ns)   --->   "%result_2_1_1 = fadd float %result_2_1, %tmp_10_1_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 31> : 7.26ns
ST_31 : Operation 122 [2/5] (7.25ns)   --->   "%result_2_1_1 = fadd float %result_2_1, %tmp_10_1_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 32> : 7.26ns
ST_32 : Operation 123 [1/5] (7.25ns)   --->   "%result_2_1_1 = fadd float %result_2_1, %tmp_10_1_1" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 33> : 7.26ns
ST_33 : Operation 124 [5/5] (7.25ns)   --->   "%result_2_1_2 = fadd float %result_2_1_1, %A_load_5" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 34> : 7.26ns
ST_34 : Operation 125 [4/5] (7.25ns)   --->   "%result_2_1_2 = fadd float %result_2_1_1, %A_load_5" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 35> : 7.26ns
ST_35 : Operation 126 [3/5] (7.25ns)   --->   "%result_2_1_2 = fadd float %result_2_1_1, %A_load_5" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 36> : 7.26ns
ST_36 : Operation 127 [2/5] (7.25ns)   --->   "%result_2_1_2 = fadd float %result_2_1_1, %A_load_5" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 37> : 7.26ns
ST_37 : Operation 128 [1/5] (7.25ns)   --->   "%result_2_1_2 = fadd float %result_2_1_1, %A_load_5" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 38> : 0.00ns

 <State 39> : 8.40ns
ST_39 : Operation 129 [1/1] (0.00ns)   --->   "%A_addr_7 = getelementptr [9 x float]* %A, i64 0, i64 7" [edge_detection/edge_detection.cpp:8]
ST_39 : Operation 130 [5/5] (8.39ns)   --->   "%result_2_2 = fadd float %result_2_1_2, %tmp_10_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_39 : Operation 131 [2/2] (2.32ns)   --->   "%A_load_7 = load float* %A_addr_7, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 40> : 7.26ns
ST_40 : Operation 132 [4/5] (7.25ns)   --->   "%result_2_2 = fadd float %result_2_1_2, %tmp_10_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_40 : Operation 133 [1/2] (2.32ns)   --->   "%A_load_7 = load float* %A_addr_7, align 4" [edge_detection/edge_detection.cpp:8]   --->   Core 37 'RAM' <Latency = 1> <II = 1> <Delay = 2.32> <Storage> <Opcode : 'load' 'store'> <Ports = 2> <Width = 32> <Depth = 9> <RAM>

 <State 41> : 7.26ns
ST_41 : Operation 134 [3/5] (7.25ns)   --->   "%result_2_2 = fadd float %result_2_1_2, %tmp_10_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 42> : 7.26ns
ST_42 : Operation 135 [2/5] (7.25ns)   --->   "%result_2_2 = fadd float %result_2_1_2, %tmp_10_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 43> : 7.26ns
ST_43 : Operation 136 [1/5] (7.25ns)   --->   "%result_2_2 = fadd float %result_2_1_2, %tmp_10_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 44> : 7.26ns
ST_44 : Operation 137 [5/5] (7.25ns)   --->   "%result_2_2_1 = fadd float %result_2_2, %A_load_7" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 45> : 7.26ns
ST_45 : Operation 138 [4/5] (7.25ns)   --->   "%result_2_2_1 = fadd float %result_2_2, %A_load_7" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 46> : 7.26ns
ST_46 : Operation 139 [3/5] (7.25ns)   --->   "%result_2_2_1 = fadd float %result_2_2, %A_load_7" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 47> : 7.26ns
ST_47 : Operation 140 [2/5] (7.25ns)   --->   "%result_2_2_1 = fadd float %result_2_2, %A_load_7" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 48> : 7.26ns
ST_48 : Operation 141 [1/5] (7.25ns)   --->   "%result_2_2_1 = fadd float %result_2_2, %A_load_7" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 49> : 0.00ns

 <State 50> : 8.40ns
ST_50 : Operation 142 [5/5] (8.39ns)   --->   "%result_2_2_2 = fadd float %result_2_2_1, %tmp_10_2_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 51> : 7.26ns
ST_51 : Operation 143 [4/5] (7.25ns)   --->   "%result_2_2_2 = fadd float %result_2_2_1, %tmp_10_2_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 52> : 7.26ns
ST_52 : Operation 144 [3/5] (7.25ns)   --->   "%result_2_2_2 = fadd float %result_2_2_1, %tmp_10_2_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 53> : 7.26ns
ST_53 : Operation 145 [2/5] (7.25ns)   --->   "%result_2_2_2 = fadd float %result_2_2_1, %tmp_10_2_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>

 <State 54> : 7.26ns
ST_54 : Operation 146 [1/5] (7.25ns)   --->   "%result_2_2_2 = fadd float %result_2_2_1, %tmp_10_2_2" [edge_detection/edge_detection.cpp:8]   --->   Core 99 'FAddSub' <Latency = 4> <II = 1> <Delay = 7.25> <FuncUnit> <Opcode : 'fadd' 'fsub'> <InPorts = 2> <OutPorts = 1>
ST_54 : Operation 147 [1/1] (0.00ns)   --->   "ret float %result_2_2_2" [edge_detection/edge_detection.cpp:9]


============================================================
+ Verbose Summary: Binding
============================================================
STG Binding: 
---------------- STG Properties BEGIN ----------------
- Is combinational: 0
- Is one-state seq: 0
- Is datapath-only: 0
- Is pipelined: 1
- Is top level: 0
Port [ Return ] is wired: 1; IO mode=ap_ctrl_hs:ce=0
Port [ A]:  wired=1; compound=1; hidden=0; nouse=0; global=0; static=0; extern=0; dir=0; type=1; pingpong=0; private_global=0; MemPort=[11]; IO mode=ap_memory:ce=0
---------------- STG Properties END ------------------

---------------- Datapath Model BEGIN ----------------

<LifeTime>
<method=bitvector/>
A_addr       (getelementptr) [ 0010000000000000000000000000000000000000000000000000000]
A_addr_2     (getelementptr) [ 0001000000000000000000000000000000000000000000000000000]
A_load       (load         ) [ 0001110000000000000000000000000000000000000000000000000]
A_addr_4     (getelementptr) [ 0000100000000000000000000000000000000000000000000000000]
A_load_2     (load         ) [ 0100111000000000000000000000000000000000000000000000000]
A_addr_6     (getelementptr) [ 0000010000000000000000000000000000000000000000000000000]
A_load_4     (load         ) [ 0110011100000000000000000000000000000000000000000000000]
A_addr_8     (getelementptr) [ 0100001000000000000000000000000000000000000000000000000]
tmp_s        (fmul         ) [ 0111111111100000000000000000000000000000000000000000000]
A_load_6     (load         ) [ 0111001110000000000000000000000000000000000000000000000]
A_addr_1     (getelementptr) [ 0010000100000000000000000000000000000000000000000000000]
tmp_10_0_2   (fmul         ) [ 0111110111111111111111000000000000000000000000000000000]
A_load_8     (load         ) [ 0011100111000000000000000000000000000000000000000000000]
A_load_1     (load         ) [ 0111110011111111000000000000000000000000000000000000000]
tmp_10_1_1   (fmul         ) [ 0111110011111111111111111111111110000000000000000000000]
tmp_10_2     (fmul         ) [ 0111110001111111111111111111111111111111111100000000000]
tmp_10_2_2   (fmul         ) [ 0111110000111111111111111111111111111111111111111111111]
result_2     (fadd         ) [ 0111110000011111000000000000000000000000000000000000000]
result_2_0_1 (fadd         ) [ 0111110000000000111111000000000000000000000000000000000]
A_addr_3     (getelementptr) [ 0001000000000000001000000000000000000000000000000000000]
A_load_3     (load         ) [ 0111110000000000000111111110000000000000000000000000000]
result_2_0_2 (fadd         ) [ 0111110000000000000000111110000000000000000000000000000]
result_2_1   (fadd         ) [ 0111110000000000000000000001111110000000000000000000000]
A_addr_5     (getelementptr) [ 0000100000000000000000000000010000000000000000000000000]
A_load_5     (load         ) [ 0111110000000000000000000000001111111100000000000000000]
result_2_1_1 (fadd         ) [ 0111110000000000000000000000000001111100000000000000000]
result_2_1_2 (fadd         ) [ 0111110000000000000000000000000000000011111100000000000]
A_addr_7     (getelementptr) [ 0000010000000000000000000000000000000000100000000000000]
A_load_7     (load         ) [ 0111110000000000000000000000000000000000011111111000000]
result_2_2   (fadd         ) [ 0111110000000000000000000000000000000000000011111000000]
result_2_2_1 (fadd         ) [ 0111110000000000000000000000000000000000000000000111111]
result_2_2_2 (fadd         ) [ 0000000000000000000000000000000000000000000000000000000]
StgValue_147 (ret          ) [ 0000000000000000000000000000000000000000000000000000000]
</LifeTime>

<model>

<comp_list>
<comp id="0" class="1000" name="A">
<pin_list>
<pin id="1" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name="A"/><MemPortTyVec>1 1 </MemPortTyVec>
</StgValue>
</bind>
</comp>

<comp id="2" class="1001" name="const_2">
<pin_list>
<pin id="3" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="4" class="1001" name="const_4">
<pin_list>
<pin id="5" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="6" class="1001" name="const_6">
<pin_list>
<pin id="7" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="8" class="1001" name="const_8">
<pin_list>
<pin id="9" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="10" class="1001" name="const_10">
<pin_list>
<pin id="11" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="12" class="1001" name="const_12">
<pin_list>
<pin id="13" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="14" class="1001" name="const_14">
<pin_list>
<pin id="15" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="16" class="1001" name="const_16">
<pin_list>
<pin id="17" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="18" class="1001" name="const_18">
<pin_list>
<pin id="19" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="20" class="1001" name="const_20">
<pin_list>
<pin id="21" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="22" class="1001" name="const_22">
<pin_list>
<pin id="23" dir="1" index="0" bw="1" slack="0"/>
</pin_list>
<bind>
<StgValue><ssdm name=""/></StgValue>
</bind>
</comp>

<comp id="24" class="1004" name="A_addr_gep_fu_24">
<pin_list>
<pin id="25" dir="0" index="0" bw="32" slack="0"/>
<pin id="26" dir="0" index="1" bw="1" slack="0"/>
<pin id="27" dir="0" index="2" bw="1" slack="0"/>
<pin id="28" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr/1 "/>
</bind>
</comp>

<comp id="32" class="1004" name="grp_access_fu_32">
<pin_list>
<pin id="33" dir="0" index="0" bw="4" slack="0"/>
<pin id="34" dir="0" index="1" bw="32" slack="2147483647"/>
<pin id="81" dir="0" index="3" bw="4" slack="0"/>
<pin id="82" dir="0" index="4" bw="32" slack="2147483647"/>
<pin id="35" dir="1" index="2" bw="32" slack="0"/>
<pin id="83" dir="1" index="5" bw="32" slack="4"/>
</pin_list>
<bind>
<opcode="load(27) " fcode="load"/>
<opset="A_load/1 A_load_2/2 A_load_4/3 A_load_6/4 A_load_8/5 A_load_1/6 A_load_3/17 A_load_5/28 A_load_7/39 "/>
</bind>
</comp>

<comp id="37" class="1004" name="A_addr_2_gep_fu_37">
<pin_list>
<pin id="38" dir="0" index="0" bw="32" slack="0"/>
<pin id="39" dir="0" index="1" bw="1" slack="0"/>
<pin id="40" dir="0" index="2" bw="3" slack="0"/>
<pin id="41" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr_2/2 "/>
</bind>
</comp>

<comp id="46" class="1004" name="A_addr_4_gep_fu_46">
<pin_list>
<pin id="47" dir="0" index="0" bw="32" slack="0"/>
<pin id="48" dir="0" index="1" bw="1" slack="0"/>
<pin id="49" dir="0" index="2" bw="4" slack="0"/>
<pin id="50" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr_4/3 "/>
</bind>
</comp>

<comp id="55" class="1004" name="A_addr_6_gep_fu_55">
<pin_list>
<pin id="56" dir="0" index="0" bw="32" slack="0"/>
<pin id="57" dir="0" index="1" bw="1" slack="0"/>
<pin id="58" dir="0" index="2" bw="4" slack="0"/>
<pin id="59" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr_6/4 "/>
</bind>
</comp>

<comp id="64" class="1004" name="A_addr_8_gep_fu_64">
<pin_list>
<pin id="65" dir="0" index="0" bw="32" slack="0"/>
<pin id="66" dir="0" index="1" bw="1" slack="0"/>
<pin id="67" dir="0" index="2" bw="5" slack="0"/>
<pin id="68" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr_8/5 "/>
</bind>
</comp>

<comp id="73" class="1004" name="A_addr_1_gep_fu_73">
<pin_list>
<pin id="74" dir="0" index="0" bw="32" slack="0"/>
<pin id="75" dir="0" index="1" bw="1" slack="0"/>
<pin id="76" dir="0" index="2" bw="1" slack="0"/>
<pin id="77" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr_1/6 "/>
</bind>
</comp>

<comp id="85" class="1004" name="A_addr_3_gep_fu_85">
<pin_list>
<pin id="86" dir="0" index="0" bw="32" slack="0"/>
<pin id="87" dir="0" index="1" bw="1" slack="0"/>
<pin id="88" dir="0" index="2" bw="3" slack="0"/>
<pin id="89" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr_3/17 "/>
</bind>
</comp>

<comp id="94" class="1004" name="A_addr_5_gep_fu_94">
<pin_list>
<pin id="95" dir="0" index="0" bw="32" slack="0"/>
<pin id="96" dir="0" index="1" bw="1" slack="0"/>
<pin id="97" dir="0" index="2" bw="4" slack="0"/>
<pin id="98" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr_5/28 "/>
</bind>
</comp>

<comp id="103" class="1004" name="A_addr_7_gep_fu_103">
<pin_list>
<pin id="104" dir="0" index="0" bw="32" slack="0"/>
<pin id="105" dir="0" index="1" bw="1" slack="0"/>
<pin id="106" dir="0" index="2" bw="4" slack="0"/>
<pin id="107" dir="1" index="3" bw="4" slack="0"/>
</pin_list>
<bind>
<opcode="getelementptr(29) " fcode="getelementptr"/>
<opset="A_addr_7/39 "/>
</bind>
</comp>

<comp id="112" class="1004" name="grp_fu_112">
<pin_list>
<pin id="113" dir="0" index="0" bw="32" slack="1"/>
<pin id="114" dir="0" index="1" bw="32" slack="0"/>
<pin id="115" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2/6 result_2_0_2/17 result_2_1_1/28 result_2_2/39 result_2_2_2/50 "/>
</bind>
</comp>

<comp id="117" class="1004" name="grp_fu_117">
<pin_list>
<pin id="118" dir="0" index="0" bw="32" slack="1"/>
<pin id="119" dir="0" index="1" bw="32" slack="4"/>
<pin id="120" dir="1" index="2" bw="32" slack="2"/>
</pin_list>
<bind>
<opcode="fadd(9) " fcode="fadd"/>
<opset="result_2_0_1/11 result_2_1/22 result_2_1_2/33 result_2_2_1/44 "/>
</bind>
</comp>

<comp id="121" class="1004" name="grp_fu_121">
<pin_list>
<pin id="122" dir="0" index="0" bw="32" slack="0"/>
<pin id="123" dir="0" index="1" bw="32" slack="0"/>
<pin id="124" dir="1" index="2" bw="32" slack="1"/>
</pin_list>
<bind>
<opcode="fmul(13) " fcode="fmul"/>
<opset="tmp_s/2 tmp_10_0_2/3 tmp_10_1_1/4 tmp_10_2/5 tmp_10_2_2/6 "/>
</bind>
</comp>

<comp id="128" class="1005" name="A_addr_reg_128">
<pin_list>
<pin id="129" dir="0" index="0" bw="4" slack="1"/>
<pin id="130" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr "/>
</bind>
</comp>

<comp id="133" class="1005" name="A_addr_2_reg_133">
<pin_list>
<pin id="134" dir="0" index="0" bw="4" slack="1"/>
<pin id="135" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_2 "/>
</bind>
</comp>

<comp id="138" class="1005" name="A_load_reg_138">
<pin_list>
<pin id="139" dir="0" index="0" bw="32" slack="1"/>
<pin id="140" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_load "/>
</bind>
</comp>

<comp id="143" class="1005" name="A_addr_4_reg_143">
<pin_list>
<pin id="144" dir="0" index="0" bw="4" slack="1"/>
<pin id="145" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_4 "/>
</bind>
</comp>

<comp id="148" class="1005" name="A_load_2_reg_148">
<pin_list>
<pin id="149" dir="0" index="0" bw="32" slack="1"/>
<pin id="150" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_load_2 "/>
</bind>
</comp>

<comp id="153" class="1005" name="A_addr_6_reg_153">
<pin_list>
<pin id="154" dir="0" index="0" bw="4" slack="1"/>
<pin id="155" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_6 "/>
</bind>
</comp>

<comp id="158" class="1005" name="A_load_4_reg_158">
<pin_list>
<pin id="159" dir="0" index="0" bw="32" slack="1"/>
<pin id="160" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_load_4 "/>
</bind>
</comp>

<comp id="163" class="1005" name="A_addr_8_reg_163">
<pin_list>
<pin id="164" dir="0" index="0" bw="4" slack="1"/>
<pin id="165" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_8 "/>
</bind>
</comp>

<comp id="168" class="1005" name="tmp_s_reg_168">
<pin_list>
<pin id="169" dir="0" index="0" bw="32" slack="1"/>
<pin id="170" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="tmp_s "/>
</bind>
</comp>

<comp id="173" class="1005" name="A_load_6_reg_173">
<pin_list>
<pin id="174" dir="0" index="0" bw="32" slack="1"/>
<pin id="175" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_load_6 "/>
</bind>
</comp>

<comp id="178" class="1005" name="A_addr_1_reg_178">
<pin_list>
<pin id="179" dir="0" index="0" bw="4" slack="1"/>
<pin id="180" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_1 "/>
</bind>
</comp>

<comp id="183" class="1005" name="tmp_10_0_2_reg_183">
<pin_list>
<pin id="184" dir="0" index="0" bw="32" slack="11"/>
<pin id="185" dir="1" index="1" bw="32" slack="11"/>
</pin_list>
<bind>
<opset="tmp_10_0_2 "/>
</bind>
</comp>

<comp id="188" class="1005" name="A_load_8_reg_188">
<pin_list>
<pin id="189" dir="0" index="0" bw="32" slack="1"/>
<pin id="190" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="A_load_8 "/>
</bind>
</comp>

<comp id="193" class="1005" name="A_load_1_reg_193">
<pin_list>
<pin id="194" dir="0" index="0" bw="32" slack="4"/>
<pin id="195" dir="1" index="1" bw="32" slack="4"/>
</pin_list>
<bind>
<opset="A_load_1 "/>
</bind>
</comp>

<comp id="198" class="1005" name="tmp_10_1_1_reg_198">
<pin_list>
<pin id="199" dir="0" index="0" bw="32" slack="21"/>
<pin id="200" dir="1" index="1" bw="32" slack="21"/>
</pin_list>
<bind>
<opset="tmp_10_1_1 "/>
</bind>
</comp>

<comp id="203" class="1005" name="tmp_10_2_reg_203">
<pin_list>
<pin id="204" dir="0" index="0" bw="32" slack="31"/>
<pin id="205" dir="1" index="1" bw="32" slack="31"/>
</pin_list>
<bind>
<opset="tmp_10_2 "/>
</bind>
</comp>

<comp id="208" class="1005" name="tmp_10_2_2_reg_208">
<pin_list>
<pin id="209" dir="0" index="0" bw="32" slack="41"/>
<pin id="210" dir="1" index="1" bw="32" slack="41"/>
</pin_list>
<bind>
<opset="tmp_10_2_2 "/>
</bind>
</comp>

<comp id="213" class="1005" name="result_2_reg_213">
<pin_list>
<pin id="214" dir="0" index="0" bw="32" slack="1"/>
<pin id="215" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2 "/>
</bind>
</comp>

<comp id="218" class="1005" name="result_2_0_1_reg_218">
<pin_list>
<pin id="219" dir="0" index="0" bw="32" slack="2"/>
<pin id="220" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="result_2_0_1 "/>
</bind>
</comp>

<comp id="223" class="1005" name="A_addr_3_reg_223">
<pin_list>
<pin id="224" dir="0" index="0" bw="4" slack="1"/>
<pin id="225" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_3 "/>
</bind>
</comp>

<comp id="228" class="1005" name="A_load_3_reg_228">
<pin_list>
<pin id="229" dir="0" index="0" bw="32" slack="4"/>
<pin id="230" dir="1" index="1" bw="32" slack="4"/>
</pin_list>
<bind>
<opset="A_load_3 "/>
</bind>
</comp>

<comp id="233" class="1005" name="result_2_0_2_reg_233">
<pin_list>
<pin id="234" dir="0" index="0" bw="32" slack="1"/>
<pin id="235" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_0_2 "/>
</bind>
</comp>

<comp id="238" class="1005" name="result_2_1_reg_238">
<pin_list>
<pin id="239" dir="0" index="0" bw="32" slack="2"/>
<pin id="240" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="result_2_1 "/>
</bind>
</comp>

<comp id="243" class="1005" name="A_addr_5_reg_243">
<pin_list>
<pin id="244" dir="0" index="0" bw="4" slack="1"/>
<pin id="245" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_5 "/>
</bind>
</comp>

<comp id="248" class="1005" name="A_load_5_reg_248">
<pin_list>
<pin id="249" dir="0" index="0" bw="32" slack="4"/>
<pin id="250" dir="1" index="1" bw="32" slack="4"/>
</pin_list>
<bind>
<opset="A_load_5 "/>
</bind>
</comp>

<comp id="253" class="1005" name="result_2_1_1_reg_253">
<pin_list>
<pin id="254" dir="0" index="0" bw="32" slack="1"/>
<pin id="255" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_1_1 "/>
</bind>
</comp>

<comp id="258" class="1005" name="result_2_1_2_reg_258">
<pin_list>
<pin id="259" dir="0" index="0" bw="32" slack="2"/>
<pin id="260" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="result_2_1_2 "/>
</bind>
</comp>

<comp id="263" class="1005" name="A_addr_7_reg_263">
<pin_list>
<pin id="264" dir="0" index="0" bw="4" slack="1"/>
<pin id="265" dir="1" index="1" bw="4" slack="1"/>
</pin_list>
<bind>
<opset="A_addr_7 "/>
</bind>
</comp>

<comp id="268" class="1005" name="A_load_7_reg_268">
<pin_list>
<pin id="269" dir="0" index="0" bw="32" slack="4"/>
<pin id="270" dir="1" index="1" bw="32" slack="4"/>
</pin_list>
<bind>
<opset="A_load_7 "/>
</bind>
</comp>

<comp id="273" class="1005" name="result_2_2_reg_273">
<pin_list>
<pin id="274" dir="0" index="0" bw="32" slack="1"/>
<pin id="275" dir="1" index="1" bw="32" slack="1"/>
</pin_list>
<bind>
<opset="result_2_2 "/>
</bind>
</comp>

<comp id="278" class="1005" name="result_2_2_1_reg_278">
<pin_list>
<pin id="279" dir="0" index="0" bw="32" slack="2"/>
<pin id="280" dir="1" index="1" bw="32" slack="2"/>
</pin_list>
<bind>
<opset="result_2_2_1 "/>
</bind>
</comp>

</comp_list>

<net_list>
<net id="29"><net_src comp="0" pin="0"/><net_sink comp="24" pin=0"/></net>

<net id="30"><net_src comp="2" pin="0"/><net_sink comp="24" pin=1"/></net>

<net id="31"><net_src comp="2" pin="0"/><net_sink comp="24" pin=2"/></net>

<net id="36"><net_src comp="24" pin="3"/><net_sink comp="32" pin=0"/></net>

<net id="42"><net_src comp="0" pin="0"/><net_sink comp="37" pin=0"/></net>

<net id="43"><net_src comp="2" pin="0"/><net_sink comp="37" pin=1"/></net>

<net id="44"><net_src comp="4" pin="0"/><net_sink comp="37" pin=2"/></net>

<net id="45"><net_src comp="37" pin="3"/><net_sink comp="32" pin=0"/></net>

<net id="51"><net_src comp="0" pin="0"/><net_sink comp="46" pin=0"/></net>

<net id="52"><net_src comp="2" pin="0"/><net_sink comp="46" pin=1"/></net>

<net id="53"><net_src comp="8" pin="0"/><net_sink comp="46" pin=2"/></net>

<net id="54"><net_src comp="46" pin="3"/><net_sink comp="32" pin=0"/></net>

<net id="60"><net_src comp="0" pin="0"/><net_sink comp="55" pin=0"/></net>

<net id="61"><net_src comp="2" pin="0"/><net_sink comp="55" pin=1"/></net>

<net id="62"><net_src comp="10" pin="0"/><net_sink comp="55" pin=2"/></net>

<net id="63"><net_src comp="55" pin="3"/><net_sink comp="32" pin=0"/></net>

<net id="69"><net_src comp="0" pin="0"/><net_sink comp="64" pin=0"/></net>

<net id="70"><net_src comp="2" pin="0"/><net_sink comp="64" pin=1"/></net>

<net id="71"><net_src comp="14" pin="0"/><net_sink comp="64" pin=2"/></net>

<net id="72"><net_src comp="64" pin="3"/><net_sink comp="32" pin=0"/></net>

<net id="78"><net_src comp="0" pin="0"/><net_sink comp="73" pin=0"/></net>

<net id="79"><net_src comp="2" pin="0"/><net_sink comp="73" pin=1"/></net>

<net id="80"><net_src comp="16" pin="0"/><net_sink comp="73" pin=2"/></net>

<net id="84"><net_src comp="73" pin="3"/><net_sink comp="32" pin=3"/></net>

<net id="90"><net_src comp="0" pin="0"/><net_sink comp="85" pin=0"/></net>

<net id="91"><net_src comp="2" pin="0"/><net_sink comp="85" pin=1"/></net>

<net id="92"><net_src comp="18" pin="0"/><net_sink comp="85" pin=2"/></net>

<net id="93"><net_src comp="85" pin="3"/><net_sink comp="32" pin=3"/></net>

<net id="99"><net_src comp="0" pin="0"/><net_sink comp="94" pin=0"/></net>

<net id="100"><net_src comp="2" pin="0"/><net_sink comp="94" pin=1"/></net>

<net id="101"><net_src comp="20" pin="0"/><net_sink comp="94" pin=2"/></net>

<net id="102"><net_src comp="94" pin="3"/><net_sink comp="32" pin=3"/></net>

<net id="108"><net_src comp="0" pin="0"/><net_sink comp="103" pin=0"/></net>

<net id="109"><net_src comp="2" pin="0"/><net_sink comp="103" pin=1"/></net>

<net id="110"><net_src comp="22" pin="0"/><net_sink comp="103" pin=2"/></net>

<net id="111"><net_src comp="103" pin="3"/><net_sink comp="32" pin=3"/></net>

<net id="116"><net_src comp="6" pin="0"/><net_sink comp="112" pin=1"/></net>

<net id="125"><net_src comp="32" pin="2"/><net_sink comp="121" pin=0"/></net>

<net id="126"><net_src comp="6" pin="0"/><net_sink comp="121" pin=1"/></net>

<net id="127"><net_src comp="12" pin="0"/><net_sink comp="121" pin=1"/></net>

<net id="131"><net_src comp="24" pin="3"/><net_sink comp="128" pin=0"/></net>

<net id="132"><net_src comp="128" pin="1"/><net_sink comp="32" pin=0"/></net>

<net id="136"><net_src comp="37" pin="3"/><net_sink comp="133" pin=0"/></net>

<net id="137"><net_src comp="133" pin="1"/><net_sink comp="32" pin=0"/></net>

<net id="141"><net_src comp="32" pin="2"/><net_sink comp="138" pin=0"/></net>

<net id="142"><net_src comp="138" pin="1"/><net_sink comp="121" pin=0"/></net>

<net id="146"><net_src comp="46" pin="3"/><net_sink comp="143" pin=0"/></net>

<net id="147"><net_src comp="143" pin="1"/><net_sink comp="32" pin=0"/></net>

<net id="151"><net_src comp="32" pin="2"/><net_sink comp="148" pin=0"/></net>

<net id="152"><net_src comp="148" pin="1"/><net_sink comp="121" pin=0"/></net>

<net id="156"><net_src comp="55" pin="3"/><net_sink comp="153" pin=0"/></net>

<net id="157"><net_src comp="153" pin="1"/><net_sink comp="32" pin=0"/></net>

<net id="161"><net_src comp="32" pin="2"/><net_sink comp="158" pin=0"/></net>

<net id="162"><net_src comp="158" pin="1"/><net_sink comp="121" pin=0"/></net>

<net id="166"><net_src comp="64" pin="3"/><net_sink comp="163" pin=0"/></net>

<net id="167"><net_src comp="163" pin="1"/><net_sink comp="32" pin=0"/></net>

<net id="171"><net_src comp="121" pin="2"/><net_sink comp="168" pin=0"/></net>

<net id="172"><net_src comp="168" pin="1"/><net_sink comp="112" pin=0"/></net>

<net id="176"><net_src comp="32" pin="2"/><net_sink comp="173" pin=0"/></net>

<net id="177"><net_src comp="173" pin="1"/><net_sink comp="121" pin=0"/></net>

<net id="181"><net_src comp="73" pin="3"/><net_sink comp="178" pin=0"/></net>

<net id="182"><net_src comp="178" pin="1"/><net_sink comp="32" pin=3"/></net>

<net id="186"><net_src comp="121" pin="2"/><net_sink comp="183" pin=0"/></net>

<net id="187"><net_src comp="183" pin="1"/><net_sink comp="112" pin=1"/></net>

<net id="191"><net_src comp="32" pin="2"/><net_sink comp="188" pin=0"/></net>

<net id="192"><net_src comp="188" pin="1"/><net_sink comp="121" pin=0"/></net>

<net id="196"><net_src comp="32" pin="5"/><net_sink comp="193" pin=0"/></net>

<net id="197"><net_src comp="193" pin="1"/><net_sink comp="117" pin=1"/></net>

<net id="201"><net_src comp="121" pin="2"/><net_sink comp="198" pin=0"/></net>

<net id="202"><net_src comp="198" pin="1"/><net_sink comp="112" pin=1"/></net>

<net id="206"><net_src comp="121" pin="2"/><net_sink comp="203" pin=0"/></net>

<net id="207"><net_src comp="203" pin="1"/><net_sink comp="112" pin=1"/></net>

<net id="211"><net_src comp="121" pin="2"/><net_sink comp="208" pin=0"/></net>

<net id="212"><net_src comp="208" pin="1"/><net_sink comp="112" pin=1"/></net>

<net id="216"><net_src comp="112" pin="2"/><net_sink comp="213" pin=0"/></net>

<net id="217"><net_src comp="213" pin="1"/><net_sink comp="117" pin=0"/></net>

<net id="221"><net_src comp="117" pin="2"/><net_sink comp="218" pin=0"/></net>

<net id="222"><net_src comp="218" pin="1"/><net_sink comp="112" pin=0"/></net>

<net id="226"><net_src comp="85" pin="3"/><net_sink comp="223" pin=0"/></net>

<net id="227"><net_src comp="223" pin="1"/><net_sink comp="32" pin=3"/></net>

<net id="231"><net_src comp="32" pin="5"/><net_sink comp="228" pin=0"/></net>

<net id="232"><net_src comp="228" pin="1"/><net_sink comp="117" pin=1"/></net>

<net id="236"><net_src comp="112" pin="2"/><net_sink comp="233" pin=0"/></net>

<net id="237"><net_src comp="233" pin="1"/><net_sink comp="117" pin=0"/></net>

<net id="241"><net_src comp="117" pin="2"/><net_sink comp="238" pin=0"/></net>

<net id="242"><net_src comp="238" pin="1"/><net_sink comp="112" pin=0"/></net>

<net id="246"><net_src comp="94" pin="3"/><net_sink comp="243" pin=0"/></net>

<net id="247"><net_src comp="243" pin="1"/><net_sink comp="32" pin=3"/></net>

<net id="251"><net_src comp="32" pin="5"/><net_sink comp="248" pin=0"/></net>

<net id="252"><net_src comp="248" pin="1"/><net_sink comp="117" pin=1"/></net>

<net id="256"><net_src comp="112" pin="2"/><net_sink comp="253" pin=0"/></net>

<net id="257"><net_src comp="253" pin="1"/><net_sink comp="117" pin=0"/></net>

<net id="261"><net_src comp="117" pin="2"/><net_sink comp="258" pin=0"/></net>

<net id="262"><net_src comp="258" pin="1"/><net_sink comp="112" pin=0"/></net>

<net id="266"><net_src comp="103" pin="3"/><net_sink comp="263" pin=0"/></net>

<net id="267"><net_src comp="263" pin="1"/><net_sink comp="32" pin=3"/></net>

<net id="271"><net_src comp="32" pin="5"/><net_sink comp="268" pin=0"/></net>

<net id="272"><net_src comp="268" pin="1"/><net_sink comp="117" pin=1"/></net>

<net id="276"><net_src comp="112" pin="2"/><net_sink comp="273" pin=0"/></net>

<net id="277"><net_src comp="273" pin="1"/><net_sink comp="117" pin=0"/></net>

<net id="281"><net_src comp="117" pin="2"/><net_sink comp="278" pin=0"/></net>

<net id="282"><net_src comp="278" pin="1"/><net_sink comp="112" pin=0"/></net>

</net_list>

</model> 
---------------- Datapath Model END ------------------

* FSMD analyzer results:
  - Output states:
	Port: A | {}
 - Input state : 
	Port: compute_pixel : A | {1 2 3 4 5 6 7 17 18 28 29 39 40 }
  - Chain level:
	State 1
		A_load : 1
	State 2
		tmp_s : 1
		A_load_2 : 1
	State 3
		tmp_10_0_2 : 1
		A_load_4 : 1
	State 4
		tmp_10_1_1 : 1
		A_load_6 : 1
	State 5
		tmp_10_2 : 1
		A_load_8 : 1
	State 6
		A_load_1 : 1
		tmp_10_2_2 : 1
	State 7
	State 8
	State 9
	State 10
	State 11
	State 12
	State 13
	State 14
	State 15
	State 16
	State 17
		A_load_3 : 1
	State 18
	State 19
	State 20
	State 21
	State 22
	State 23
	State 24
	State 25
	State 26
	State 27
	State 28
		A_load_5 : 1
	State 29
	State 30
	State 31
	State 32
	State 33
	State 34
	State 35
	State 36
	State 37
	State 38
	State 39
		A_load_7 : 1
	State 40
	State 41
	State 42
	State 43
	State 44
	State 45
	State 46
	State 47
	State 48
	State 49
	State 50
	State 51
	State 52
	State 53
	State 54
		StgValue_147 : 1


============================================================
+ Verbose Summary: Datapath Resource usage 
============================================================

* Functional unit list:
|----------|----------------|---------|---------|---------|
| Operation| Functional Unit|  DSP48E |    FF   |   LUT   |
|----------|----------------|---------|---------|---------|
|   fadd   |   grp_fu_112   |    2    |   205   |   390   |
|          |   grp_fu_117   |    2    |   205   |   390   |
|----------|----------------|---------|---------|---------|
|   fmul   |   grp_fu_121   |    3    |   143   |   321   |
|----------|----------------|---------|---------|---------|
|   Total  |                |    7    |   553   |   1101  |
|----------|----------------|---------|---------|---------|

Memories:
N/A

* Register list:
+--------------------+--------+
|                    |   FF   |
+--------------------+--------+
|  A_addr_1_reg_178  |    4   |
|  A_addr_2_reg_133  |    4   |
|  A_addr_3_reg_223  |    4   |
|  A_addr_4_reg_143  |    4   |
|  A_addr_5_reg_243  |    4   |
|  A_addr_6_reg_153  |    4   |
|  A_addr_7_reg_263  |    4   |
|  A_addr_8_reg_163  |    4   |
|   A_addr_reg_128   |    4   |
|  A_load_1_reg_193  |   32   |
|  A_load_2_reg_148  |   32   |
|  A_load_3_reg_228  |   32   |
|  A_load_4_reg_158  |   32   |
|  A_load_5_reg_248  |   32   |
|  A_load_6_reg_173  |   32   |
|  A_load_7_reg_268  |   32   |
|  A_load_8_reg_188  |   32   |
|   A_load_reg_138   |   32   |
|result_2_0_1_reg_218|   32   |
|result_2_0_2_reg_233|   32   |
|result_2_1_1_reg_253|   32   |
|result_2_1_2_reg_258|   32   |
| result_2_1_reg_238 |   32   |
|result_2_2_1_reg_278|   32   |
| result_2_2_reg_273 |   32   |
|  result_2_reg_213  |   32   |
| tmp_10_0_2_reg_183 |   32   |
| tmp_10_1_1_reg_198 |   32   |
| tmp_10_2_2_reg_208 |   32   |
|  tmp_10_2_reg_203  |   32   |
|    tmp_s_reg_168   |   32   |
+--------------------+--------+
|        Total       |   740  |
+--------------------+--------+

* Multiplexer (MUX) list: 
|------------------|------|------|------|--------||---------||---------|
|       Comp       |  Pin | Size |  BW  | S x BW ||  Delay  ||   LUT   |
|------------------|------|------|------|--------||---------||---------|
| grp_access_fu_32 |  p0  |  10  |   4  |   40   ||    47   |
| grp_access_fu_32 |  p3  |   8  |   4  |   32   ||    41   |
|    grp_fu_112    |  p0  |   5  |  32  |   160  ||    27   |
|    grp_fu_112    |  p1  |   5  |  32  |   160  ||    27   |
|    grp_fu_117    |  p0  |   4  |  32  |   128  ||    21   |
|    grp_fu_117    |  p1  |   4  |  32  |   128  ||    21   |
|    grp_fu_121    |  p0  |   6  |  32  |   192  ||    33   |
|    grp_fu_121    |  p1  |   2  |  32  |   64   |
|------------------|------|------|------|--------||---------||---------|
|       Total      |      |      |      |   904  || 15.3067 ||   217   |
|------------------|------|------|------|--------||---------||---------|



* Summary:
+-----------+--------+--------+--------+--------+
|           | DSP48E |  Delay |   FF   |   LUT  |
+-----------+--------+--------+--------+--------+
|  Function |    7   |    -   |   553  |  1101  |
|   Memory  |    -   |    -   |    -   |    -   |
|Multiplexer|    -   |   15   |    -   |   217  |
|  Register |    -   |    -   |   740  |    -   |
+-----------+--------+--------+--------+--------+
|   Total   |    7   |   15   |  1293  |  1318  |
+-----------+--------+--------+--------+--------+