xilinx.com BlockDiagram design_1 1.00.a isTop true DDR CAN_DEBUG false TIMEPERIOD_PS 1250 MEMORY_TYPE COMPONENTS DATA_WIDTH 8 CS_ENABLED true DATA_MASK_ENABLED true SLOT Single MEM_ADDR_MAP ROW_COLUMN_BANK BURST_LENGTH 8 AXI_ARBITRATION_SCHEME TDM CAS_LATENCY 11 CAS_WRITE_LATENCY 11 FIXED_IO CAN_DEBUG false BlockDiagram :vivado.xilinx.com: xilinx.com BlockDiagram design_1_imp 1.00.a apint_arith_0 design_1_apint_arith_0_0 processing_system7_0 design_1_processing_system7_0_0 0x1FFFFFFF 533.333313 0.025 0.028 -0.009 -0.061 0.41 0.411 0.341 0.358 666.666667 200.000000 50 50 50 100.000000 150.000000 50.000000 666.666687 533.333374 10.158730 200.000000 10.000000 125.000000 10.000000 50.000000 50.000000 10.000000 10.000000 111.111115 200.000000 200.000000 100.000000 10.000000 10.000000 10.000000 111.111115 111.111115 111.111115 111.111115 111.111115 111.111115 100000000 10000000 10000000 10000000 1 1 1 1 1 1 1 1 1 1 LVCMOS 3.3V LVCMOS 1.8V DDR 3 8 MT41J128M16 HA-15E 1 1 1 1 1 MIO 1 .. 6 1 MIO 1 .. 6 0 x4 0 0 1 MIO 16 .. 27 1 MIO 52 .. 53 1 Share reset pin 0 1 MIO 40 .. 45 1 MIO 47 1 MIO 46 0 1 MIO 48 .. 49 0 1 EMIO 0 1 MIO 28 .. 39 1 Share reset pin 0 0 1 1 MIO 1000 Mbps disabled LVCMOS 3.3V slow disabled LVCMOS 3.3V fast LVCMOS 3.3V fast LVCMOS 3.3V fast LVCMOS 3.3V fast LVCMOS 3.3V fast LVCMOS 3.3V fast LVCMOS 3.3V slow LVCMOS 3.3V fast disabled LVCMOS 3.3V slow disabled LVCMOS 3.3V slow disabled LVCMOS 3.3V slow disabled LVCMOS 3.3V slow disabled LVCMOS 3.3V slow disabled LVCMOS 3.3V slow disabled LVCMOS 3.3V slow disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V fast disabled LVCMOS 1.8V slow disabled LVCMOS 1.8V slow disabled LVCMOS 1.8V slow disabled LVCMOS 1.8V slow disabled LVCMOS 1.8V slow disabled LVCMOS 1.8V slow disabled LVCMOS 1.8V slow disabled LVCMOS 1.8V slow ZedBoard GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0 gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#wp#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio 1 ps7_0_axi_periph design_1_ps7_0_axi_periph_0 1 xilinx.com:ip:axi_interconnect:2.1 rst_ps7_0_100M design_1_rst_ps7_0_100M_0 processing_system7_0_M_AXI_GP0 ps7_0_axi_periph_M00_AXI processing_system7_0_FCLK_CLK0 processing_system7_0_FCLK_RESET0_N rst_ps7_0_100M_peripheral_aresetn rst_ps7_0_100M_interconnect_aresetn xilinx.com BlockDiagram/design_1_imp ps7_0_axi_periph 1.00.a S00_AXI M00_AXI CLK.ACLK Clk Clock CLK ACLK ASSOCIATED_RESET ARESETN RST.ARESETN Reset Reset RST ARESETN CLK.S00_ACLK Clk Clock CLK S00_ACLK ASSOCIATED_BUSIF S00_AXI ASSOCIATED_RESET S00_ARESETN RST.S00_ARESETN Reset Reset RST S00_ARESETN CLK.M00_ACLK Clk Clock CLK M00_ACLK ASSOCIATED_BUSIF M00_AXI ASSOCIATED_RESET M00_ARESETN RST.M00_ARESETN Reset Reset RST M00_ARESETN BlockDiagram :vivado.xilinx.com: ACLK in ARESETN in S00_ACLK in S00_ARESETN in M00_ACLK in M00_ARESETN in xilinx.com BlockDiagram/design_1_imp ps7_0_axi_periph_imp 1.00.a s00_couplers ps7_0_axi_periph_ACLK_net ps7_0_axi_periph_ARESETN_net S00_ACLK_1 S00_ARESETN_1 xilinx.com BlockDiagram/design_1_imp/ps7_0_axi_periph_imp s00_couplers 1.00.a M_AXI S_AXI CLK.M_ACLK Clk Clock CLK M_ACLK ASSOCIATED_BUSIF M_AXI ASSOCIATED_RESET M_ARESETN RST.M_ARESETN Reset Reset RST M_ARESETN CLK.S_ACLK Clk Clock CLK S_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_ARESETN RST.S_ARESETN Reset Reset RST S_ARESETN BlockDiagram :vivado.xilinx.com: M_ACLK in M_ARESETN in S_ACLK in S_ARESETN in xilinx.com BlockDiagram/design_1_imp/ps7_0_axi_periph_imp s00_couplers_imp 1.00.a auto_pc design_1_auto_pc_0 AXI3 AXI4LITE S_ACLK_1 S_ARESETN_1 xilinx.com Addressing/processing_system7_0 processing_system7 5.5 M_AXI_GP0 0x40000000 Data 4G 32 SEG_apint_arith_0_Reg /apint_arith_0/s_axi_AXILiteS/Reg 0x43C00000 64K