Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Tue Dec 5 12:22:58 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_timing_summary -warn_on_violation -max_paths 10 -file vga_sprite_timing_summary_routed.rpt -rpx vga_sprite_timing_summary_routed.rpx | Design : vga_sprite | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 0 input ports with no input delay specified. There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 14 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 32.118 0.000 0 78 0.082 0.000 0 78 3.000 0.000 0 51 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk_100MHz {0.000 5.000} 10.000 100.000 clk_out_clk_100MHz_to_25MHz {0.000 20.000} 40.000 25.000 clkfbout_clk_100MHz_to_25MHz {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk_100MHz 3.000 0.000 0 1 clk_out_clk_100MHz_to_25MHz 32.118 0.000 0 78 0.082 0.000 0 78 19.500 0.000 0 47 clkfbout_clk_100MHz_to_25MHz 7.845 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk_100MHz To Clock: clk_100MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100MHz } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out_clk_100MHz_to_25MHz To Clock: clk_out_clk_100MHz_to_25MHz Setup : 0 Failing Endpoints, Worst Slack 32.118ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.082ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 32.118ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.643ns (logic 1.842ns (24.100%) route 5.801ns (75.900%)) Logic Levels: 7 (CARRY4=2 LUT3=1 LUT4=1 LUT6=3) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 r video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 2.405 4.396 ghost[0]1[8] SLICE_X106Y42 LUT6 (Prop_lut6_I5_O) 0.295 4.691 r video_sig[11]_i_45/O net (fo=5, routed) 0.708 5.399 video_sig[11]_i_45_n_0 SLICE_X107Y42 LUT6 (Prop_lut6_I5_O) 0.124 5.523 r video_sig[4]_i_5/O net (fo=1, routed) 0.646 6.169 video_sig[4]_i_5_n_0 SLICE_X110Y42 LUT6 (Prop_lut6_I5_O) 0.124 6.293 r video_sig[4]_i_2/O net (fo=1, routed) 0.484 6.777 video_sig[4]_i_2_n_0 SLICE_X110Y42 LUT3 (Prop_lut3_I2_O) 0.124 6.901 r video_sig[4]_i_1/O net (fo=1, routed) 0.000 6.901 p_1_in[4] SLICE_X110Y42 FDRE r video_sig_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X110Y42 FDRE r video_sig_reg[4]/C clock pessimism 0.462 39.087 clock uncertainty -0.098 38.989 SLICE_X110Y42 FDRE (Setup_fdre_C_D) 0.029 39.018 video_sig_reg[4] ------------------------------------------------------------------- required time 39.018 arrival time -6.901 ------------------------------------------------------------------- slack 32.118 Slack (MET) : 32.136ns (required time - arrival time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[10]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.775ns (logic 2.393ns (30.777%) route 5.382ns (69.223%)) Logic Levels: 7 (CARRY4=2 LUT1=1 LUT3=1 LUT5=1 LUT6=2) Clock Path Skew: -0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.733ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.879 -0.733 clk_25MHz SLICE_X106Y49 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y49 FDRE (Prop_fdre_C_Q) 0.419 -0.314 f hor_cnt_reg[1]/Q net (fo=16, routed) 0.391 0.078 hor_cnt_reg_n_0_[1] SLICE_X108Y49 LUT1 (Prop_lut1_I0_O) 0.297 0.375 r video_sig[11]_i_37/O net (fo=1, routed) 0.000 0.375 video_sig[11]_i_37_n_0 SLICE_X108Y49 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.533 0.908 r video_sig_reg[11]_i_14/CO[3] net (fo=1, routed) 0.001 0.908 video_sig_reg[11]_i_14_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.127 r video_sig_reg[11]_i_5/O[0] net (fo=96, routed) 2.406 3.533 ghost[0]1[4] SLICE_X113Y45 LUT5 (Prop_lut5_I1_O) 0.323 3.856 r video_sig[10]_i_12/O net (fo=2, routed) 0.674 4.531 video_sig[10]_i_12_n_0 SLICE_X112Y45 LUT6 (Prop_lut6_I0_O) 0.326 4.857 r video_sig[10]_i_5/O net (fo=3, routed) 0.969 5.825 video_sig[10]_i_5_n_0 SLICE_X111Y44 LUT6 (Prop_lut6_I3_O) 0.124 5.949 r video_sig[10]_i_2/O net (fo=1, routed) 0.941 6.891 video_sig[10]_i_2_n_0 SLICE_X111Y41 LUT3 (Prop_lut3_I2_O) 0.152 7.043 r video_sig[10]_i_1/O net (fo=1, routed) 0.000 7.043 p_1_in[10] SLICE_X111Y41 FDRE r video_sig_reg[10]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X111Y41 FDRE r video_sig_reg[10]/C clock pessimism 0.577 39.201 clock uncertainty -0.098 39.104 SLICE_X111Y41 FDRE (Setup_fdre_C_D) 0.075 39.179 video_sig_reg[10] ------------------------------------------------------------------- required time 39.179 arrival time -7.043 ------------------------------------------------------------------- slack 32.136 Slack (MET) : 32.231ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.530ns (logic 1.842ns (24.462%) route 5.688ns (75.538%)) Logic Levels: 7 (CARRY4=2 LUT3=1 LUT4=1 LUT6=3) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 f video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 2.192 4.182 ghost[0]1[8] SLICE_X109Y41 LUT6 (Prop_lut6_I0_O) 0.295 4.477 r video_sig[8]_i_12/O net (fo=3, routed) 0.595 5.072 video_sig[8]_i_12_n_0 SLICE_X109Y42 LUT6 (Prop_lut6_I0_O) 0.124 5.196 r video_sig[0]_i_3/O net (fo=1, routed) 0.801 5.997 video_sig[0]_i_3_n_0 SLICE_X110Y42 LUT6 (Prop_lut6_I1_O) 0.124 6.121 r video_sig[0]_i_2/O net (fo=1, routed) 0.542 6.663 video_sig[0]_i_2_n_0 SLICE_X111Y41 LUT3 (Prop_lut3_I2_O) 0.124 6.787 r video_sig[0]_i_1/O net (fo=1, routed) 0.000 6.787 p_1_in[0] SLICE_X111Y41 FDRE r video_sig_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X111Y41 FDRE r video_sig_reg[0]/C clock pessimism 0.462 39.087 clock uncertainty -0.098 38.989 SLICE_X111Y41 FDRE (Setup_fdre_C_D) 0.029 39.018 video_sig_reg[0] ------------------------------------------------------------------- required time 39.018 arrival time -6.787 ------------------------------------------------------------------- slack 32.231 Slack (MET) : 32.243ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.519ns (logic 1.842ns (24.497%) route 5.677ns (75.503%)) Logic Levels: 7 (CARRY4=2 LUT3=1 LUT4=1 LUT6=3) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 r video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 2.405 4.396 ghost[0]1[8] SLICE_X106Y42 LUT6 (Prop_lut6_I5_O) 0.295 4.691 r video_sig[11]_i_45/O net (fo=5, routed) 0.844 5.535 video_sig[11]_i_45_n_0 SLICE_X108Y42 LUT6 (Prop_lut6_I5_O) 0.124 5.659 r video_sig[1]_i_4/O net (fo=1, routed) 0.580 6.239 video_sig[1]_i_4_n_0 SLICE_X111Y42 LUT6 (Prop_lut6_I5_O) 0.124 6.363 r video_sig[1]_i_2/O net (fo=1, routed) 0.290 6.653 video_sig[1]_i_2_n_0 SLICE_X111Y41 LUT3 (Prop_lut3_I2_O) 0.124 6.777 r video_sig[1]_i_1/O net (fo=1, routed) 0.000 6.777 p_1_in[1] SLICE_X111Y41 FDRE r video_sig_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X111Y41 FDRE r video_sig_reg[1]/C clock pessimism 0.462 39.087 clock uncertainty -0.098 38.989 SLICE_X111Y41 FDRE (Setup_fdre_C_D) 0.031 39.020 video_sig_reg[1] ------------------------------------------------------------------- required time 39.020 arrival time -6.777 ------------------------------------------------------------------- slack 32.243 Slack (MET) : 32.246ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.560ns (logic 1.870ns (24.734%) route 5.690ns (75.266%)) Logic Levels: 7 (CARRY4=2 LUT3=1 LUT4=1 LUT6=3) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 r video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 2.405 4.396 ghost[0]1[8] SLICE_X106Y42 LUT6 (Prop_lut6_I5_O) 0.295 4.691 r video_sig[11]_i_45/O net (fo=5, routed) 0.771 5.462 video_sig[11]_i_45_n_0 SLICE_X110Y43 LUT6 (Prop_lut6_I5_O) 0.124 5.586 r video_sig[5]_i_4/O net (fo=1, routed) 0.159 5.745 video_sig[5]_i_4_n_0 SLICE_X110Y43 LUT6 (Prop_lut6_I5_O) 0.124 5.869 r video_sig[5]_i_2/O net (fo=1, routed) 0.797 6.666 video_sig[5]_i_2_n_0 SLICE_X110Y42 LUT3 (Prop_lut3_I2_O) 0.152 6.818 r video_sig[5]_i_1/O net (fo=1, routed) 0.000 6.818 p_1_in[5] SLICE_X110Y42 FDRE r video_sig_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X110Y42 FDRE r video_sig_reg[5]/C clock pessimism 0.462 39.087 clock uncertainty -0.098 38.989 SLICE_X110Y42 FDRE (Setup_fdre_C_D) 0.075 39.064 video_sig_reg[5] ------------------------------------------------------------------- required time 39.064 arrival time -6.818 ------------------------------------------------------------------- slack 32.246 Slack (MET) : 32.392ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[6]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.371ns (logic 1.842ns (24.989%) route 5.529ns (75.011%)) Logic Levels: 7 (CARRY4=2 LUT3=1 LUT4=1 LUT6=3) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 r video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 1.223 3.213 ghost[0]1[8] SLICE_X110Y46 LUT6 (Prop_lut6_I0_O) 0.295 3.508 r video_sig[6]_i_5/O net (fo=2, routed) 0.670 4.178 video_sig[6]_i_5_n_0 SLICE_X110Y46 LUT6 (Prop_lut6_I0_O) 0.124 4.302 r video_sig[6]_i_3/O net (fo=1, routed) 0.992 5.294 video_sig[6]_i_3_n_0 SLICE_X111Y44 LUT6 (Prop_lut6_I1_O) 0.124 5.418 r video_sig[6]_i_2/O net (fo=1, routed) 1.086 6.505 video_sig[6]_i_2_n_0 SLICE_X111Y41 LUT3 (Prop_lut3_I2_O) 0.124 6.629 r video_sig[6]_i_1/O net (fo=1, routed) 0.000 6.629 p_1_in[6] SLICE_X111Y41 FDRE r video_sig_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X111Y41 FDRE r video_sig_reg[6]/C clock pessimism 0.462 39.087 clock uncertainty -0.098 38.989 SLICE_X111Y41 FDRE (Setup_fdre_C_D) 0.031 39.020 video_sig_reg[6] ------------------------------------------------------------------- required time 39.020 arrival time -6.629 ------------------------------------------------------------------- slack 32.392 Slack (MET) : 32.418ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.256ns (logic 2.252ns (31.036%) route 5.004ns (68.964%)) Logic Levels: 8 (CARRY4=2 LUT4=1 LUT5=1 LUT6=2 MUXF7=1 MUXF8=1) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 r video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 2.263 4.253 ghost[0]1[8] SLICE_X108Y44 LUT6 (Prop_lut6_I0_O) 0.295 4.548 r video_sig[11]_i_46/O net (fo=1, routed) 0.000 4.548 video_sig[11]_i_46_n_0 SLICE_X108Y44 MUXF7 (Prop_muxf7_I0_O) 0.241 4.789 r video_sig_reg[11]_i_39/O net (fo=1, routed) 0.000 4.789 video_sig_reg[11]_i_39_n_0 SLICE_X108Y44 MUXF8 (Prop_muxf8_I0_O) 0.098 4.887 r video_sig_reg[11]_i_20/O net (fo=2, routed) 0.360 5.247 video_sig_reg[11]_i_20_n_0 SLICE_X109Y44 LUT6 (Prop_lut6_I0_O) 0.319 5.566 r video_sig[7]_i_3/O net (fo=1, routed) 0.149 5.715 video_sig[7]_i_3_n_0 SLICE_X109Y44 LUT5 (Prop_lut5_I4_O) 0.124 5.839 r video_sig[7]_i_1/O net (fo=2, routed) 0.674 6.513 p_1_in[7] SLICE_X110Y41 FDRE r video_sig_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X110Y41 FDRE r video_sig_reg[7]/C clock pessimism 0.462 39.087 clock uncertainty -0.098 38.989 SLICE_X110Y41 FDRE (Setup_fdre_C_D) -0.058 38.931 video_sig_reg[7] ------------------------------------------------------------------- required time 38.931 arrival time -6.513 ------------------------------------------------------------------- slack 32.418 Slack (MET) : 32.480ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.327ns (logic 1.868ns (25.494%) route 5.459ns (74.506%)) Logic Levels: 7 (CARRY4=2 LUT3=1 LUT4=1 LUT6=3) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 r video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 1.680 3.671 ghost[0]1[8] SLICE_X112Y43 LUT6 (Prop_lut6_I0_O) 0.295 3.966 r video_sig[9]_i_9/O net (fo=1, routed) 0.680 4.646 video_sig[9]_i_9_n_0 SLICE_X112Y43 LUT6 (Prop_lut6_I5_O) 0.124 4.770 r video_sig[9]_i_3/O net (fo=3, routed) 0.827 5.597 video_sig[9]_i_3_n_0 SLICE_X111Y43 LUT6 (Prop_lut6_I0_O) 0.124 5.721 r video_sig[9]_i_2/O net (fo=1, routed) 0.714 6.435 video_sig[9]_i_2_n_0 SLICE_X111Y41 LUT3 (Prop_lut3_I2_O) 0.150 6.585 r video_sig[9]_i_1/O net (fo=1, routed) 0.000 6.585 p_1_in[9] SLICE_X111Y41 FDRE r video_sig_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X111Y41 FDRE r video_sig_reg[9]/C clock pessimism 0.462 39.087 clock uncertainty -0.098 38.989 SLICE_X111Y41 FDRE (Setup_fdre_C_D) 0.075 39.064 video_sig_reg[9] ------------------------------------------------------------------- required time 39.064 arrival time -6.585 ------------------------------------------------------------------- slack 32.480 Slack (MET) : 32.498ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.262ns (logic 1.842ns (25.366%) route 5.420ns (74.634%)) Logic Levels: 7 (CARRY4=2 LUT4=1 LUT5=3 LUT6=1) Clock Path Skew: -0.172ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.376ns = ( 38.624 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 r video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 2.405 4.396 ghost[0]1[8] SLICE_X106Y42 LUT6 (Prop_lut6_I5_O) 0.295 4.691 r video_sig[11]_i_45/O net (fo=5, routed) 0.647 5.338 video_sig[11]_i_45_n_0 SLICE_X108Y43 LUT5 (Prop_lut5_I4_O) 0.124 5.462 r video_sig[11]_i_22/O net (fo=1, routed) 0.466 5.928 video_sig[11]_i_22_n_0 SLICE_X108Y43 LUT5 (Prop_lut5_I4_O) 0.124 6.052 r video_sig[11]_i_6/O net (fo=1, routed) 0.343 6.395 video_sig[11]_i_6_n_0 SLICE_X109Y43 LUT5 (Prop_lut5_I4_O) 0.124 6.519 r video_sig[11]_i_2/O net (fo=1, routed) 0.000 6.519 p_1_in[11] SLICE_X109Y43 FDRE r video_sig_reg[11]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.697 38.624 clk_25MHz SLICE_X109Y43 FDRE r video_sig_reg[11]/C clock pessimism 0.462 39.086 clock uncertainty -0.098 38.988 SLICE_X109Y43 FDRE (Setup_fdre_C_D) 0.029 39.017 video_sig_reg[11] ------------------------------------------------------------------- required time 39.017 arrival time -6.519 ------------------------------------------------------------------- slack 32.498 Slack (MET) : 32.515ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 7.246ns (logic 1.842ns (25.422%) route 5.404ns (74.578%)) Logic Levels: 7 (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=2) Clock Path Skew: -0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.375ns = ( 38.625 - 40.000 ) Source Clock Delay (SCD): -0.743ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.869 -0.743 clk_25MHz SLICE_X110Y50 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y50 FDRE (Prop_fdre_C_Q) 0.456 -0.287 r ver_cnt_reg[1]/Q net (fo=31, routed) 1.558 1.271 ver_cnt_reg_n_0_[1] SLICE_X108Y50 LUT4 (Prop_lut4_I1_O) 0.124 1.395 r video_sig[11]_i_16/O net (fo=1, routed) 0.000 1.395 video_sig[11]_i_16_n_0 SLICE_X108Y50 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.376 1.771 r video_sig_reg[11]_i_5/CO[3] net (fo=1, routed) 0.000 1.771 video_sig_reg[11]_i_5_n_0 SLICE_X108Y51 CARRY4 (Prop_carry4_CI_O[0]) 0.219 1.990 f video_sig_reg[11]_i_11/O[0] net (fo=91, routed) 2.192 4.182 ghost[0]1[8] SLICE_X109Y41 LUT6 (Prop_lut6_I0_O) 0.295 4.477 r video_sig[8]_i_12/O net (fo=3, routed) 0.814 5.291 video_sig[8]_i_12_n_0 SLICE_X109Y43 LUT6 (Prop_lut6_I0_O) 0.124 5.415 r video_sig[8]_i_5/O net (fo=1, routed) 0.437 5.852 video_sig[8]_i_5_n_0 SLICE_X110Y42 LUT3 (Prop_lut3_I2_O) 0.124 5.976 r video_sig[8]_i_2/O net (fo=1, routed) 0.403 6.379 video_sig[8]_i_2_n_0 SLICE_X111Y42 LUT5 (Prop_lut5_I2_O) 0.124 6.503 r video_sig[8]_i_1/O net (fo=1, routed) 0.000 6.503 p_1_in[8] SLICE_X111Y42 FDRE r video_sig_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.698 38.625 clk_25MHz SLICE_X111Y42 FDRE r video_sig_reg[8]/C clock pessimism 0.462 39.087 clock uncertainty -0.098 38.989 SLICE_X111Y42 FDRE (Setup_fdre_C_D) 0.029 39.018 video_sig_reg[8] ------------------------------------------------------------------- required time 39.018 arrival time -6.503 ------------------------------------------------------------------- slack 32.515 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.082ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.443ns (logic 0.226ns (51.029%) route 0.217ns (48.971%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.268ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.777ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.507ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.640 -0.539 clk_25MHz SLICE_X106Y49 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r hor_cnt_reg[1]/Q net (fo=16, routed) 0.217 -0.194 hor_cnt_reg_n_0_[1] SLICE_X107Y50 LUT5 (Prop_lut5_I2_O) 0.098 -0.096 r out_reg[0]_i_1/O net (fo=1, routed) 0.000 -0.096 out_reg[0] SLICE_X107Y50 FDRE r out_reg_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.908 -0.777 clk_25MHz SLICE_X107Y50 FDRE r out_reg_reg[0]/C clock pessimism 0.507 -0.270 SLICE_X107Y50 FDRE (Hold_fdre_C_D) 0.092 -0.178 out_reg_reg[0] ------------------------------------------------------------------- required time 0.178 arrival time -0.096 ------------------------------------------------------------------- slack 0.082 Slack (MET) : 0.115ns (arrival time - required time) Source: hor_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: A[1]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.484ns (logic 0.183ns (37.784%) route 0.301ns (62.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.268ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.777ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.507ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.640 -0.539 clk_25MHz SLICE_X109Y49 FDRE r hor_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r hor_cnt_reg[2]/Q net (fo=15, routed) 0.301 -0.096 hor_cnt_reg_n_0_[2] SLICE_X109Y50 LUT5 (Prop_lut5_I4_O) 0.042 -0.054 r hor_cnt[4]_i_1/O net (fo=2, routed) 0.000 -0.054 hor_cnt[4]_i_1_n_0 SLICE_X109Y50 FDRE r A[1]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.908 -0.777 clk_25MHz SLICE_X109Y50 FDRE r A[1]/C clock pessimism 0.507 -0.270 SLICE_X109Y50 FDRE (Hold_fdre_C_D) 0.101 -0.169 A[1] ------------------------------------------------------------------- required time 0.169 arrival time -0.054 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.172ns (arrival time - required time) Source: out_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.537ns (logic 0.186ns (34.649%) route 0.351ns (65.351%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.273ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.774ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): -0.507ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.638 -0.541 clk_25MHz SLICE_X107Y50 FDRE r out_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r out_reg_reg[0]/Q net (fo=11, routed) 0.351 -0.049 out_reg_reg_n_0_[0] SLICE_X110Y46 LUT5 (Prop_lut5_I0_O) 0.045 -0.004 r video_sig[2]_i_1/O net (fo=1, routed) 0.000 -0.004 p_1_in[2] SLICE_X110Y46 FDRE r video_sig_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.911 -0.774 clk_25MHz SLICE_X110Y46 FDRE r video_sig_reg[2]/C clock pessimism 0.507 -0.267 SLICE_X110Y46 FDRE (Hold_fdre_C_D) 0.092 -0.175 video_sig_reg[2] ------------------------------------------------------------------- required time 0.175 arrival time -0.004 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.176ns (arrival time - required time) Source: out_reg_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[3]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.281ns (logic 0.186ns (66.187%) route 0.095ns (33.813%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.777ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): -0.249ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.638 -0.541 clk_25MHz SLICE_X107Y51 FDRE r out_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X107Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r out_reg_reg[4]/Q net (fo=1, routed) 0.095 -0.305 data1[3] SLICE_X106Y51 LUT5 (Prop_lut5_I4_O) 0.045 -0.260 r out_reg[3]_i_1/O net (fo=1, routed) 0.000 -0.260 out_reg[3] SLICE_X106Y51 FDRE r out_reg_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.908 -0.777 clk_25MHz SLICE_X106Y51 FDRE r out_reg_reg[3]/C clock pessimism 0.249 -0.528 SLICE_X106Y51 FDRE (Hold_fdre_C_D) 0.092 -0.436 out_reg_reg[3] ------------------------------------------------------------------- required time 0.436 arrival time -0.260 ------------------------------------------------------------------- slack 0.176 Slack (MET) : 0.178ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.538ns (logic 0.226ns (41.983%) route 0.312ns (58.017%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.268ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.777ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.507ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.640 -0.539 clk_25MHz SLICE_X106Y49 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r hor_cnt_reg[1]/Q net (fo=16, routed) 0.312 -0.098 hor_cnt_reg_n_0_[1] SLICE_X107Y51 LUT5 (Prop_lut5_I2_O) 0.098 -0.000 r out_reg[1]_i_1/O net (fo=1, routed) 0.000 -0.000 out_reg[1] SLICE_X107Y51 FDRE r out_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.908 -0.777 clk_25MHz SLICE_X107Y51 FDRE r out_reg_reg[1]/C clock pessimism 0.507 -0.270 SLICE_X107Y51 FDRE (Hold_fdre_C_D) 0.092 -0.178 out_reg_reg[1] ------------------------------------------------------------------- required time 0.178 arrival time -0.000 ------------------------------------------------------------------- slack 0.178 Slack (MET) : 0.198ns (arrival time - required time) Source: hor_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.302ns (logic 0.186ns (61.598%) route 0.116ns (38.402%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.774ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.248ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.640 -0.539 clk_25MHz SLICE_X106Y49 FDRE r hor_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r hor_cnt_reg[0]/Q net (fo=15, routed) 0.116 -0.282 hor_cnt_reg_n_0_[0] SLICE_X107Y49 LUT5 (Prop_lut5_I1_O) 0.045 -0.237 r out_reg[5]_i_1/O net (fo=1, routed) 0.000 -0.237 out_reg[5] SLICE_X107Y49 FDRE r out_reg_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.911 -0.774 clk_25MHz SLICE_X107Y49 FDRE r out_reg_reg[5]/C clock pessimism 0.248 -0.526 SLICE_X107Y49 FDRE (Hold_fdre_C_D) 0.091 -0.435 out_reg_reg[5] ------------------------------------------------------------------- required time 0.435 arrival time -0.237 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.233ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.593ns (logic 0.226ns (38.091%) route 0.367ns (61.909%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.268ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.777ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.507ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.640 -0.539 clk_25MHz SLICE_X106Y49 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r hor_cnt_reg[1]/Q net (fo=16, routed) 0.367 -0.043 hor_cnt_reg_n_0_[1] SLICE_X107Y51 LUT5 (Prop_lut5_I2_O) 0.098 0.055 r out_reg[4]_i_1/O net (fo=1, routed) 0.000 0.055 out_reg[4] SLICE_X107Y51 FDRE r out_reg_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.908 -0.777 clk_25MHz SLICE_X107Y51 FDRE r out_reg_reg[4]/C clock pessimism 0.507 -0.270 SLICE_X107Y51 FDRE (Hold_fdre_C_D) 0.092 -0.178 out_reg_reg[4] ------------------------------------------------------------------- required time 0.178 arrival time 0.055 ------------------------------------------------------------------- slack 0.233 Slack (MET) : 0.242ns (arrival time - required time) Source: ver_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.334ns (logic 0.227ns (68.027%) route 0.107ns (31.973%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.774ns Source Clock Delay (SCD): -0.540ns Clock Pessimism Removal (CPR): -0.234ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.639 -0.540 clk_25MHz SLICE_X110Y51 FDRE r ver_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y51 FDRE (Prop_fdre_C_Q) 0.128 -0.412 r ver_cnt_reg[2]/Q net (fo=27, routed) 0.107 -0.305 ver_cnt_reg_n_0_[2] SLICE_X110Y51 LUT6 (Prop_lut6_I2_O) 0.099 -0.206 r ver_cnt[5]_i_1/O net (fo=1, routed) 0.000 -0.206 ver_cnt[5]_i_1_n_0 SLICE_X110Y51 FDRE r ver_cnt_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.911 -0.774 clk_25MHz SLICE_X110Y51 FDRE r ver_cnt_reg[5]/C clock pessimism 0.234 -0.540 SLICE_X110Y51 FDRE (Hold_fdre_C_D) 0.092 -0.448 ver_cnt_reg[5] ------------------------------------------------------------------- required time 0.448 arrival time -0.206 ------------------------------------------------------------------- slack 0.242 Slack (MET) : 0.250ns (arrival time - required time) Source: hor_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[6]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.358ns (logic 0.186ns (51.997%) route 0.172ns (48.003%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.774ns Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.640 -0.539 clk_25MHz SLICE_X109Y49 FDRE r hor_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f hor_cnt_reg[2]/Q net (fo=15, routed) 0.172 -0.226 hor_cnt_reg_n_0_[2] SLICE_X107Y49 LUT6 (Prop_lut6_I3_O) 0.045 -0.181 r out_reg[6]_i_2/O net (fo=1, routed) 0.000 -0.181 out_reg[6] SLICE_X107Y49 FDRE r out_reg_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.911 -0.774 clk_25MHz SLICE_X107Y49 FDRE r out_reg_reg[6]/C clock pessimism 0.251 -0.523 SLICE_X107Y49 FDRE (Hold_fdre_C_D) 0.092 -0.431 out_reg_reg[6] ------------------------------------------------------------------- required time 0.431 arrival time -0.181 ------------------------------------------------------------------- slack 0.250 Slack (MET) : 0.258ns (arrival time - required time) Source: out_reg_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.350ns (logic 0.186ns (53.177%) route 0.164ns (46.823%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.777ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): -0.236ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.638 -0.541 clk_25MHz SLICE_X106Y51 FDRE r out_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X106Y51 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r out_reg_reg[3]/Q net (fo=1, routed) 0.164 -0.236 data1[2] SLICE_X106Y51 LUT5 (Prop_lut5_I4_O) 0.045 -0.191 r out_reg[2]_i_1/O net (fo=1, routed) 0.000 -0.191 out_reg[2] SLICE_X106Y51 FDRE r out_reg_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.908 -0.777 clk_25MHz SLICE_X106Y51 FDRE r out_reg_reg[2]/C clock pessimism 0.236 -0.541 SLICE_X106Y51 FDRE (Hold_fdre_C_D) 0.092 -0.449 out_reg_reg[2] ------------------------------------------------------------------- required time 0.449 arrival time -0.191 ------------------------------------------------------------------- slack 0.258 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out_clk_100MHz_to_25MHz Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y0 clk_converter/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X109Y49 A[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X109Y50 A[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X109Y52 A[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X108Y52 A[3]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y52 Hsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X112Y51 Vsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X106Y49 hor_cnt_reg[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X106Y49 hor_cnt_reg[1]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y50 A[1]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y52 A[2]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X108Y52 A[3]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y52 Hsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y51 Vsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y50 hor_cnt_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y52 hor_cnt_reg[5]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X110Y52 hor_cnt_reg[6]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X110Y52 hor_cnt_reg[7]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y52 hor_cnt_reg[8]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y49 A[0]/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y49 A[0]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y50 A[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y52 A[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X108Y52 A[3]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y52 Hsync_sig_reg/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y52 Hsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y51 Vsync_sig_reg/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y51 Vsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X106Y49 hor_cnt_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_100MHz_to_25MHz To Clock: clkfbout_clk_100MHz_to_25MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_100MHz_to_25MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 clk_converter/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT