----------------------------------------------------------------------------------
-- Company: 
-- Engineer: Hakkel Tamás
-- 
-- Create Date: 10/20/2017 09:30:34 AM
-- Design Name: VGA example
-- Module Name: clk_gen_test - Behavioral
-- Project Name: VGA
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_gen_test is
    Port ( Hsync : out STD_LOGIC;
           Vsync : out STD_LOGIC;
           video : out STD_LOGIC_VECTOR(11 downto 0);
           clk_100MHz : in STD_LOGIC);
end clk_gen_test;

architecture Behavioral of clk_gen_test is

component clk_wiz_0
port
 (
  clk_out1          : out    std_logic;
  clk_in1           : in     std_logic
 );
end component;

signal clk_25MHz : std_logic;
signal hor_cnt : unsigned(9 downto 0) := (others => '0');
signal ver_cnt : unsigned(9 downto 0) := (others => '0');
signal Hsync_sig : std_logic :='1';
signal Vsync_sig : std_logic :='1';
signal video_sig : std_logic_vector(11 downto 0) := (others => '0');
signal xor_sig : std_logic_vector(9 downto 0) := (others => '0');

-- Szimuláláshoz jobb, ha 10-zel leosztom az összes konstansomat
--constant hor_max : integer := 80;
--constant hor_addr_time : integer := 64;
--constant hor_front_porch : integer := 1;
--constant hor_sync_time : integer := 9;
--constant ver_max : integer := 52;
--constant ver_addr_time : integer := 48;
--constant ver_front_porch : integer := 1;
--constant ver_sync_time : integer := 0;

constant hor_max : integer := 800;
constant hor_addr_time : integer := 640;
constant hor_front_porch : integer := 16;
constant hor_sync_time : integer := 96;
constant ver_max : integer := 525;
constant ver_addr_time : integer := 480;
constant ver_front_porch : integer := 10;
constant ver_sync_time : integer := 2;

begin

process(clk_25MHz)
begin
   -- Órajelre növelem a számlálókat
   if clk_25MHz'event and clk_25MHz = '1' then
    if (hor_cnt = hor_max - 1) then
        hor_cnt <= to_unsigned(0, hor_cnt'length);
        if (ver_cnt = ver_max -1) then
            ver_cnt <= to_unsigned(0, ver_cnt'length);
        else
            ver_cnt <=  ver_cnt + 1;
        end if;
    else
        hor_cnt <=  hor_cnt + 1;
    end if;
    
    -- A vízszintes számláló (hor_cnt) alapján állítom a Hsync-et
    if (hor_cnt = hor_addr_time + hor_front_porch) then
        Hsync_sig <= '0';
    elsif (hor_cnt = hor_addr_time + hor_front_porch + hor_sync_time) then
        Hsync_sig <= '1';
    else
        Hsync_sig <= Hsync_sig;
    end if;
    
    -- A függőleges számláló (ver_cnt) alapján állítom a Vsync-et
    if (ver_cnt = ver_addr_time + ver_front_porch) then
        Vsync_sig <= '0';
    elsif (ver_cnt = ver_addr_time + ver_front_porch + ver_sync_time) then
        Vsync_sig <= '1';
    else
        Vsync_sig <= Vsync_sig;
    end if;
    
    xor_sig <= std_logic_vector(hor_cnt) xor std_logic_vector(ver_cnt);
    -- Csak akkor adok a video kimenetre bármit is, ha benne vagyok a megfelelő idősávban
    if (ver_cnt < ver_addr_time and hor_cnt < hor_addr_time) then
        video_sig <= xor_sig(1 downto 0) & xor_sig;
    else 
        video_sig <= (others => '0');
    end if;
        
   end if;
end process;

Hsync <= Hsync_sig;
Vsync <= Vsync_sig;
video <= video_sig;


clk_converter : clk_wiz_0
   port map (  
   clk_out1 => clk_25MHz,
   clk_in1 => clk_100MHz
 );

end Behavioral;