Folder Path

/7-szemeszter/FPGA/vga/vga.sim/sim_1/behav/

2 directories 22 files 74 KiB total

	Name	Size	Modified
	Up
	.Xil/	—	05/17/2022 08:09:50 PM +00:00
	xsim.dir/	—	05/17/2022 08:12:57 PM +00:00
	clk_gen_tb.tcl	449 B	05/17/2022 08:12:57 PM +00:00
	clk_gen_tb_behav.wdb	28 KiB	05/17/2022 08:12:57 PM +00:00
	clk_gen_tb_vhdl.prj	209 B	05/17/2022 08:12:57 PM +00:00
	clk_gen_tb_vlog.prj	416 B	05/17/2022 08:12:57 PM +00:00
	compile.log	881 B	05/17/2022 08:12:57 PM +00:00
	compile.sh	406 B	05/17/2022 08:12:57 PM +00:00
	elaborate.log	1.2 KiB	05/17/2022 08:12:57 PM +00:00
	elaborate.sh	386 B	05/17/2022 08:12:57 PM +00:00
	glbl.v	1.4 KiB	05/17/2022 08:12:57 PM +00:00
	simulate.log	48 B	05/17/2022 08:12:57 PM +00:00
	simulate.sh	256 B	05/17/2022 08:12:57 PM +00:00
	webtalk.jou	740 B	05/17/2022 08:12:57 PM +00:00
	webtalk.log	1.1 KiB	05/17/2022 08:12:57 PM +00:00
	webtalk_8238.backup.jou	740 B	05/17/2022 08:12:57 PM +00:00
	webtalk_8238.backup.log	1.1 KiB	05/17/2022 08:12:57 PM +00:00
	xelab.pb	2.6 KiB	05/17/2022 08:12:57 PM +00:00
	xsim.ini	16 KiB	05/17/2022 08:12:57 PM +00:00
	xsim.ini.bak	16 KiB	05/17/2022 08:12:57 PM +00:00
	xvhdl.log	344 B	05/17/2022 08:12:57 PM +00:00
	xvhdl.pb	594 B	05/17/2022 08:12:57 PM +00:00
	xvlog.log	537 B	05/17/2022 08:12:57 PM +00:00
	xvlog.pb	979 B	05/17/2022 08:12:57 PM +00:00