Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Fri Oct 20 12:03:04 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_timing_summary -warn_on_violation -max_paths 10 -file clk_gen_test_timing_summary_routed.rpt -rpx clk_gen_test_timing_summary_routed.rpx | Design : clk_gen_test | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 0 input ports with no input delay specified. There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 14 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 35.537 0.000 0 70 0.158 0.000 0 70 3.000 0.000 0 50 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk_100MHz {0.000 5.000} 10.000 100.000 clk_out1_clk_wiz_0 {0.000 19.863} 39.725 25.173 clkfbout_clk_wiz_0 {0.000 20.000} 40.000 25.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk_100MHz 3.000 0.000 0 1 clk_out1_clk_wiz_0 35.537 0.000 0 70 0.158 0.000 0 70 19.363 0.000 0 46 clkfbout_clk_wiz_0 37.845 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk_100MHz To Clock: clk_100MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100MHz } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out1_clk_wiz_0 To Clock: clk_out1_clk_wiz_0 Setup : 0 Failing Endpoints, Worst Slack 35.537ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.158ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.363ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 35.537ns (required time - arrival time) Source: ver_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: Vsync_sig_reg/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 3.571ns (logic 0.840ns (23.524%) route 2.731ns (76.476%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.382ns = ( 38.343 - 39.725 ) Source Clock Delay (SCD): -0.741ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.871 -0.741 clk_25MHz SLICE_X110Y33 FDRE r ver_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y33 FDRE (Prop_fdre_C_Q) 0.419 -0.322 r ver_cnt_reg[8]/Q net (fo=5, routed) 1.132 0.810 ver_cnt_reg_n_0_[8] SLICE_X111Y33 LUT6 (Prop_lut6_I3_O) 0.297 1.107 r Vsync_sig_i_3/O net (fo=2, routed) 0.951 2.058 Vsync_sig_i_3_n_0 SLICE_X110Y32 LUT5 (Prop_lut5_I0_O) 0.124 2.182 r Vsync_sig_i_1/O net (fo=1, routed) 0.648 2.830 Vsync_sig_i_1_n_0 SLICE_X110Y32 FDRE r Vsync_sig_reg/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.691 38.343 clk_25MHz SLICE_X110Y32 FDRE r Vsync_sig_reg/C clock pessimism 0.617 38.959 clock uncertainty -0.164 38.796 SLICE_X110Y32 FDRE (Setup_fdre_C_R) -0.429 38.367 Vsync_sig_reg ------------------------------------------------------------------- required time 38.367 arrival time -2.830 ------------------------------------------------------------------- slack 35.537 Slack (MET) : 36.163ns (required time - arrival time) Source: hor_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: ver_cnt_reg[0]/CE (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 3.169ns (logic 0.766ns (24.172%) route 2.403ns (75.828%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.380ns = ( 38.345 - 39.725 ) Source Clock Delay (SCD): -0.740ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.872 -0.740 clk_25MHz SLICE_X112Y34 FDRE r hor_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y34 FDRE (Prop_fdre_C_Q) 0.518 -0.222 r hor_cnt_reg[2]/Q net (fo=6, routed) 1.032 0.811 hor_cnt_reg_n_0_[2] SLICE_X112Y33 LUT5 (Prop_lut5_I1_O) 0.124 0.935 f hor_cnt[9]_i_2/O net (fo=6, routed) 0.677 1.612 hor_cnt[9]_i_2_n_0 SLICE_X110Y32 LUT6 (Prop_lut6_I5_O) 0.124 1.736 r ver_cnt[9]_i_1/O net (fo=10, routed) 0.693 2.429 ver_cnt SLICE_X110Y34 FDRE r ver_cnt_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.693 38.345 clk_25MHz SLICE_X110Y34 FDRE r ver_cnt_reg[0]/C clock pessimism 0.617 38.961 clock uncertainty -0.164 38.798 SLICE_X110Y34 FDRE (Setup_fdre_C_CE) -0.205 38.593 ver_cnt_reg[0] ------------------------------------------------------------------- required time 38.593 arrival time -2.429 ------------------------------------------------------------------- slack 36.163 Slack (MET) : 36.163ns (required time - arrival time) Source: hor_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: ver_cnt_reg[1]/CE (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 3.169ns (logic 0.766ns (24.172%) route 2.403ns (75.828%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.380ns = ( 38.345 - 39.725 ) Source Clock Delay (SCD): -0.740ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.872 -0.740 clk_25MHz SLICE_X112Y34 FDRE r hor_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y34 FDRE (Prop_fdre_C_Q) 0.518 -0.222 r hor_cnt_reg[2]/Q net (fo=6, routed) 1.032 0.811 hor_cnt_reg_n_0_[2] SLICE_X112Y33 LUT5 (Prop_lut5_I1_O) 0.124 0.935 f hor_cnt[9]_i_2/O net (fo=6, routed) 0.677 1.612 hor_cnt[9]_i_2_n_0 SLICE_X110Y32 LUT6 (Prop_lut6_I5_O) 0.124 1.736 r ver_cnt[9]_i_1/O net (fo=10, routed) 0.693 2.429 ver_cnt SLICE_X110Y34 FDRE r ver_cnt_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.693 38.345 clk_25MHz SLICE_X110Y34 FDRE r ver_cnt_reg[1]/C clock pessimism 0.617 38.961 clock uncertainty -0.164 38.798 SLICE_X110Y34 FDRE (Setup_fdre_C_CE) -0.205 38.593 ver_cnt_reg[1] ------------------------------------------------------------------- required time 38.593 arrival time -2.429 ------------------------------------------------------------------- slack 36.163 Slack (MET) : 36.163ns (required time - arrival time) Source: hor_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: ver_cnt_reg[2]/CE (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 3.169ns (logic 0.766ns (24.172%) route 2.403ns (75.828%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.380ns = ( 38.345 - 39.725 ) Source Clock Delay (SCD): -0.740ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.872 -0.740 clk_25MHz SLICE_X112Y34 FDRE r hor_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y34 FDRE (Prop_fdre_C_Q) 0.518 -0.222 r hor_cnt_reg[2]/Q net (fo=6, routed) 1.032 0.811 hor_cnt_reg_n_0_[2] SLICE_X112Y33 LUT5 (Prop_lut5_I1_O) 0.124 0.935 f hor_cnt[9]_i_2/O net (fo=6, routed) 0.677 1.612 hor_cnt[9]_i_2_n_0 SLICE_X110Y32 LUT6 (Prop_lut6_I5_O) 0.124 1.736 r ver_cnt[9]_i_1/O net (fo=10, routed) 0.693 2.429 ver_cnt SLICE_X110Y34 FDRE r ver_cnt_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.693 38.345 clk_25MHz SLICE_X110Y34 FDRE r ver_cnt_reg[2]/C clock pessimism 0.617 38.961 clock uncertainty -0.164 38.798 SLICE_X110Y34 FDRE (Setup_fdre_C_CE) -0.205 38.593 ver_cnt_reg[2] ------------------------------------------------------------------- required time 38.593 arrival time -2.429 ------------------------------------------------------------------- slack 36.163 Slack (MET) : 36.163ns (required time - arrival time) Source: hor_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: ver_cnt_reg[3]/CE (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 3.169ns (logic 0.766ns (24.172%) route 2.403ns (75.828%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.380ns = ( 38.345 - 39.725 ) Source Clock Delay (SCD): -0.740ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.872 -0.740 clk_25MHz SLICE_X112Y34 FDRE r hor_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y34 FDRE (Prop_fdre_C_Q) 0.518 -0.222 r hor_cnt_reg[2]/Q net (fo=6, routed) 1.032 0.811 hor_cnt_reg_n_0_[2] SLICE_X112Y33 LUT5 (Prop_lut5_I1_O) 0.124 0.935 f hor_cnt[9]_i_2/O net (fo=6, routed) 0.677 1.612 hor_cnt[9]_i_2_n_0 SLICE_X110Y32 LUT6 (Prop_lut6_I5_O) 0.124 1.736 r ver_cnt[9]_i_1/O net (fo=10, routed) 0.693 2.429 ver_cnt SLICE_X110Y34 FDRE r ver_cnt_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.693 38.345 clk_25MHz SLICE_X110Y34 FDRE r ver_cnt_reg[3]/C clock pessimism 0.617 38.961 clock uncertainty -0.164 38.798 SLICE_X110Y34 FDRE (Setup_fdre_C_CE) -0.205 38.593 ver_cnt_reg[3] ------------------------------------------------------------------- required time 38.593 arrival time -2.429 ------------------------------------------------------------------- slack 36.163 Slack (MET) : 36.216ns (required time - arrival time) Source: ver_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[10]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 2.893ns (logic 0.839ns (28.999%) route 2.054ns (71.001%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.380ns = ( 38.345 - 39.725 ) Source Clock Delay (SCD): -0.741ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.871 -0.741 clk_25MHz SLICE_X110Y33 FDRE r ver_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y33 FDRE (Prop_fdre_C_Q) 0.419 -0.322 r ver_cnt_reg[7]/Q net (fo=6, routed) 0.906 0.584 ver_cnt_reg_n_0_[7] SLICE_X111Y33 LUT4 (Prop_lut4_I3_O) 0.296 0.880 r ver_cnt[9]_i_4/O net (fo=2, routed) 0.307 1.187 ver_cnt[9]_i_4_n_0 SLICE_X111Y32 LUT5 (Prop_lut5_I0_O) 0.124 1.311 r video_sig[11]_i_1/O net (fo=12, routed) 0.842 2.153 video_sig[11]_i_1_n_0 SLICE_X113Y34 FDRE r video_sig_reg[10]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.693 38.345 clk_25MHz SLICE_X113Y34 FDRE r video_sig_reg[10]/C clock pessimism 0.617 38.961 clock uncertainty -0.164 38.798 SLICE_X113Y34 FDRE (Setup_fdre_C_R) -0.429 38.369 video_sig_reg[10] ------------------------------------------------------------------- required time 38.369 arrival time -2.153 ------------------------------------------------------------------- slack 36.216 Slack (MET) : 36.216ns (required time - arrival time) Source: ver_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[11]_lopt_replica/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 2.893ns (logic 0.839ns (28.999%) route 2.054ns (71.001%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.380ns = ( 38.345 - 39.725 ) Source Clock Delay (SCD): -0.741ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.871 -0.741 clk_25MHz SLICE_X110Y33 FDRE r ver_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y33 FDRE (Prop_fdre_C_Q) 0.419 -0.322 r ver_cnt_reg[7]/Q net (fo=6, routed) 0.906 0.584 ver_cnt_reg_n_0_[7] SLICE_X111Y33 LUT4 (Prop_lut4_I3_O) 0.296 0.880 r ver_cnt[9]_i_4/O net (fo=2, routed) 0.307 1.187 ver_cnt[9]_i_4_n_0 SLICE_X111Y32 LUT5 (Prop_lut5_I0_O) 0.124 1.311 r video_sig[11]_i_1/O net (fo=12, routed) 0.842 2.153 video_sig[11]_i_1_n_0 SLICE_X113Y34 FDRE r video_sig_reg[11]_lopt_replica/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.693 38.345 clk_25MHz SLICE_X113Y34 FDRE r video_sig_reg[11]_lopt_replica/C clock pessimism 0.617 38.961 clock uncertainty -0.164 38.798 SLICE_X113Y34 FDRE (Setup_fdre_C_R) -0.429 38.369 video_sig_reg[11]_lopt_replica ------------------------------------------------------------------- required time 38.369 arrival time -2.153 ------------------------------------------------------------------- slack 36.216 Slack (MET) : 36.259ns (required time - arrival time) Source: ver_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[4]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 2.755ns (logic 0.839ns (30.456%) route 1.916ns (69.544%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.381ns = ( 38.344 - 39.725 ) Source Clock Delay (SCD): -0.741ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.871 -0.741 clk_25MHz SLICE_X110Y33 FDRE r ver_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y33 FDRE (Prop_fdre_C_Q) 0.419 -0.322 r ver_cnt_reg[7]/Q net (fo=6, routed) 0.906 0.584 ver_cnt_reg_n_0_[7] SLICE_X111Y33 LUT4 (Prop_lut4_I3_O) 0.296 0.880 r ver_cnt[9]_i_4/O net (fo=2, routed) 0.307 1.187 ver_cnt[9]_i_4_n_0 SLICE_X111Y32 LUT5 (Prop_lut5_I0_O) 0.124 1.311 r video_sig[11]_i_1/O net (fo=12, routed) 0.703 2.014 video_sig[11]_i_1_n_0 SLICE_X112Y33 FDRE r video_sig_reg[4]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.692 38.344 clk_25MHz SLICE_X112Y33 FDRE r video_sig_reg[4]/C clock pessimism 0.617 38.960 clock uncertainty -0.164 38.797 SLICE_X112Y33 FDRE (Setup_fdre_C_R) -0.524 38.273 video_sig_reg[4] ------------------------------------------------------------------- required time 38.273 arrival time -2.014 ------------------------------------------------------------------- slack 36.259 Slack (MET) : 36.259ns (required time - arrival time) Source: ver_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[8]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 2.755ns (logic 0.839ns (30.456%) route 1.916ns (69.544%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.381ns = ( 38.344 - 39.725 ) Source Clock Delay (SCD): -0.741ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.871 -0.741 clk_25MHz SLICE_X110Y33 FDRE r ver_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y33 FDRE (Prop_fdre_C_Q) 0.419 -0.322 r ver_cnt_reg[7]/Q net (fo=6, routed) 0.906 0.584 ver_cnt_reg_n_0_[7] SLICE_X111Y33 LUT4 (Prop_lut4_I3_O) 0.296 0.880 r ver_cnt[9]_i_4/O net (fo=2, routed) 0.307 1.187 ver_cnt[9]_i_4_n_0 SLICE_X111Y32 LUT5 (Prop_lut5_I0_O) 0.124 1.311 r video_sig[11]_i_1/O net (fo=12, routed) 0.703 2.014 video_sig[11]_i_1_n_0 SLICE_X112Y33 FDRE r video_sig_reg[8]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.692 38.344 clk_25MHz SLICE_X112Y33 FDRE r video_sig_reg[8]/C clock pessimism 0.617 38.960 clock uncertainty -0.164 38.797 SLICE_X112Y33 FDRE (Setup_fdre_C_R) -0.524 38.273 video_sig_reg[8] ------------------------------------------------------------------- required time 38.273 arrival time -2.014 ------------------------------------------------------------------- slack 36.259 Slack (MET) : 36.259ns (required time - arrival time) Source: ver_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[9]/R (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 39.725ns (clk_out1_clk_wiz_0 rise@39.725ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 2.755ns (logic 0.839ns (30.456%) route 1.916ns (69.544%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.381ns = ( 38.344 - 39.725 ) Source Clock Delay (SCD): -0.741ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.164ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.320ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.871 -0.741 clk_25MHz SLICE_X110Y33 FDRE r ver_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y33 FDRE (Prop_fdre_C_Q) 0.419 -0.322 r ver_cnt_reg[7]/Q net (fo=6, routed) 0.906 0.584 ver_cnt_reg_n_0_[7] SLICE_X111Y33 LUT4 (Prop_lut4_I3_O) 0.296 0.880 r ver_cnt[9]_i_4/O net (fo=2, routed) 0.307 1.187 ver_cnt[9]_i_4_n_0 SLICE_X111Y32 LUT5 (Prop_lut5_I0_O) 0.124 1.311 r video_sig[11]_i_1/O net (fo=12, routed) 0.703 2.014 video_sig[11]_i_1_n_0 SLICE_X112Y33 FDRE r video_sig_reg[9]/R ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 39.725 39.725 r Y9 0.000 39.725 r clk_100MHz (IN) net (fo=0) 0.000 39.725 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 1.420 41.145 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.307 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 34.869 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.560 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.651 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 1.692 38.344 clk_25MHz SLICE_X112Y33 FDRE r video_sig_reg[9]/C clock pessimism 0.617 38.960 clock uncertainty -0.164 38.797 SLICE_X112Y33 FDRE (Setup_fdre_C_R) -0.524 38.273 video_sig_reg[9] ------------------------------------------------------------------- required time 38.273 arrival time -2.014 ------------------------------------------------------------------- slack 36.259 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.158ns (arrival time - required time) Source: xor_sig_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[6]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.243ns (logic 0.141ns (58.024%) route 0.102ns (41.976%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.634 -0.545 clk_25MHz SLICE_X111Y32 FDRE r xor_sig_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.404 r xor_sig_reg[6]/Q net (fo=1, routed) 0.102 -0.302 xor_sig[6] SLICE_X113Y32 FDRE r video_sig_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.903 -0.782 clk_25MHz SLICE_X113Y32 FDRE r video_sig_reg[6]/C clock pessimism 0.251 -0.531 SLICE_X113Y32 FDRE (Hold_fdre_C_D) 0.071 -0.460 video_sig_reg[6] ------------------------------------------------------------------- required time 0.460 arrival time -0.302 ------------------------------------------------------------------- slack 0.158 Slack (MET) : 0.185ns (arrival time - required time) Source: xor_sig_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.828%) route 0.116ns (45.172%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.781ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.635 -0.544 clk_25MHz SLICE_X113Y33 FDRE r xor_sig_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y33 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r xor_sig_reg[4]/Q net (fo=1, routed) 0.116 -0.286 xor_sig[4] SLICE_X112Y33 FDRE r video_sig_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.904 -0.781 clk_25MHz SLICE_X112Y33 FDRE r video_sig_reg[4]/C clock pessimism 0.250 -0.531 SLICE_X112Y33 FDRE (Hold_fdre_C_D) 0.059 -0.472 video_sig_reg[4] ------------------------------------------------------------------- required time 0.472 arrival time -0.286 ------------------------------------------------------------------- slack 0.185 Slack (MET) : 0.192ns (arrival time - required time) Source: xor_sig_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.828%) route 0.116ns (45.172%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.781ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.635 -0.544 clk_25MHz SLICE_X113Y33 FDRE r xor_sig_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y33 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r xor_sig_reg[8]/Q net (fo=1, routed) 0.116 -0.286 xor_sig[8] SLICE_X112Y33 FDRE r video_sig_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.904 -0.781 clk_25MHz SLICE_X112Y33 FDRE r video_sig_reg[8]/C clock pessimism 0.250 -0.531 SLICE_X112Y33 FDRE (Hold_fdre_C_D) 0.052 -0.479 video_sig_reg[8] ------------------------------------------------------------------- required time 0.479 arrival time -0.286 ------------------------------------------------------------------- slack 0.192 Slack (MET) : 0.203ns (arrival time - required time) Source: hor_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: xor_sig_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.295ns (logic 0.227ns (77.066%) route 0.068ns (22.934%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.781ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): -0.237ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.635 -0.544 clk_25MHz SLICE_X113Y33 FDRE r hor_cnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y33 FDRE (Prop_fdre_C_Q) 0.128 -0.416 r hor_cnt_reg[4]/Q net (fo=4, routed) 0.068 -0.348 hor_cnt_reg_n_0_[4] SLICE_X113Y33 LUT2 (Prop_lut2_I1_O) 0.099 -0.249 r xor_sig[4]_i_1/O net (fo=1, routed) 0.000 -0.249 xor_sig[4]_i_1_n_0 SLICE_X113Y33 FDRE r xor_sig_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.904 -0.781 clk_25MHz SLICE_X113Y33 FDRE r xor_sig_reg[4]/C clock pessimism 0.237 -0.544 SLICE_X113Y33 FDRE (Hold_fdre_C_D) 0.092 -0.452 xor_sig_reg[4] ------------------------------------------------------------------- required time 0.452 arrival time -0.249 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.210ns (arrival time - required time) Source: xor_sig_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[3]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.242ns (logic 0.128ns (52.946%) route 0.114ns (47.054%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.635 -0.544 clk_25MHz SLICE_X113Y33 FDRE r xor_sig_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y33 FDRE (Prop_fdre_C_Q) 0.128 -0.416 r xor_sig_reg[3]/Q net (fo=1, routed) 0.114 -0.302 xor_sig[3] SLICE_X113Y32 FDRE r video_sig_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.903 -0.782 clk_25MHz SLICE_X113Y32 FDRE r video_sig_reg[3]/C clock pessimism 0.251 -0.531 SLICE_X113Y32 FDRE (Hold_fdre_C_D) 0.019 -0.512 video_sig_reg[3] ------------------------------------------------------------------- required time 0.512 arrival time -0.302 ------------------------------------------------------------------- slack 0.210 Slack (MET) : 0.221ns (arrival time - required time) Source: xor_sig_reg[5]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.309ns (logic 0.164ns (53.051%) route 0.145ns (46.949%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.634 -0.545 clk_25MHz SLICE_X112Y32 FDRE r xor_sig_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.381 r xor_sig_reg[5]/Q net (fo=1, routed) 0.145 -0.236 xor_sig[5] SLICE_X113Y32 FDRE r video_sig_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.903 -0.782 clk_25MHz SLICE_X113Y32 FDRE r video_sig_reg[5]/C clock pessimism 0.250 -0.532 SLICE_X113Y32 FDRE (Hold_fdre_C_D) 0.075 -0.457 video_sig_reg[5] ------------------------------------------------------------------- required time 0.457 arrival time -0.236 ------------------------------------------------------------------- slack 0.221 Slack (MET) : 0.224ns (arrival time - required time) Source: xor_sig_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.302ns (logic 0.141ns (46.764%) route 0.161ns (53.236%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.781ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.634 -0.545 clk_25MHz SLICE_X111Y32 FDRE r xor_sig_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.404 r xor_sig_reg[9]/Q net (fo=1, routed) 0.161 -0.243 xor_sig[9] SLICE_X112Y33 FDRE r video_sig_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.904 -0.781 clk_25MHz SLICE_X112Y33 FDRE r video_sig_reg[9]/C clock pessimism 0.251 -0.530 SLICE_X112Y33 FDRE (Hold_fdre_C_D) 0.063 -0.467 video_sig_reg[9] ------------------------------------------------------------------- required time 0.467 arrival time -0.243 ------------------------------------------------------------------- slack 0.224 Slack (MET) : 0.242ns (arrival time - required time) Source: hor_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: hor_cnt_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.246ns (67.831%) route 0.117ns (32.169%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.237ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.634 -0.545 clk_25MHz SLICE_X112Y32 FDRE r hor_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y32 FDRE (Prop_fdre_C_Q) 0.148 -0.397 r hor_cnt_reg[7]/Q net (fo=8, routed) 0.117 -0.280 hor_cnt_reg_n_0_[7] SLICE_X112Y32 LUT6 (Prop_lut6_I2_O) 0.098 -0.182 r hor_cnt[8]_i_1/O net (fo=1, routed) 0.000 -0.182 hor_cnt[8] SLICE_X112Y32 FDRE r hor_cnt_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.903 -0.782 clk_25MHz SLICE_X112Y32 FDRE r hor_cnt_reg[8]/C clock pessimism 0.237 -0.545 SLICE_X112Y32 FDRE (Hold_fdre_C_D) 0.121 -0.424 hor_cnt_reg[8] ------------------------------------------------------------------- required time 0.424 arrival time -0.182 ------------------------------------------------------------------- slack 0.242 Slack (MET) : 0.253ns (arrival time - required time) Source: xor_sig_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: video_sig_reg[10]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.283ns (logic 0.148ns (52.311%) route 0.135ns (47.689%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.780ns Source Clock Delay (SCD): -0.543ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.636 -0.543 clk_25MHz SLICE_X112Y34 FDRE r xor_sig_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y34 FDRE (Prop_fdre_C_Q) 0.148 -0.395 r xor_sig_reg[0]/Q net (fo=2, routed) 0.135 -0.260 xor_sig[0] SLICE_X113Y34 FDRE r video_sig_reg[10]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.905 -0.780 clk_25MHz SLICE_X113Y34 FDRE r video_sig_reg[10]/C clock pessimism 0.250 -0.530 SLICE_X113Y34 FDRE (Hold_fdre_C_D) 0.017 -0.513 video_sig_reg[10] ------------------------------------------------------------------- required time 0.513 arrival time -0.260 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.256ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Destination: xor_sig_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@19.863ns period=39.725ns}) Path Group: clk_out1_clk_wiz_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.183ns (50.353%) route 0.180ns (49.647%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.780ns Source Clock Delay (SCD): -0.543ns Clock Pessimism Removal (CPR): -0.237ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.636 -0.543 clk_25MHz SLICE_X111Y34 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.402 r hor_cnt_reg[1]/Q net (fo=8, routed) 0.180 -0.221 hor_cnt_reg_n_0_[1] SLICE_X111Y34 LUT2 (Prop_lut2_I1_O) 0.042 -0.179 r xor_sig[1]_i_1/O net (fo=1, routed) 0.000 -0.179 xor_sig[1]_i_1_n_0 SLICE_X111Y34 FDRE r xor_sig_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_out1_clk_wiz_0 rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in1 Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in1_clk_wiz_0 MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out1_clk_wiz_0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=44, routed) 0.905 -0.780 clk_25MHz SLICE_X111Y34 FDRE r xor_sig_reg[1]/C clock pessimism 0.237 -0.543 SLICE_X111Y34 FDRE (Hold_fdre_C_D) 0.107 -0.436 xor_sig_reg[1] ------------------------------------------------------------------- required time 0.436 arrival time -0.179 ------------------------------------------------------------------- slack 0.256 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out1_clk_wiz_0 Waveform(ns): { 0.000 19.863 } Period(ns): 39.725 Sources: { clk_converter/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 39.725 37.570 BUFGCTRL_X0Y0 clk_converter/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 39.725 38.476 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 39.725 38.725 SLICE_X111Y33 Hsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 39.725 38.725 SLICE_X110Y32 Vsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 39.725 38.725 SLICE_X112Y34 hor_cnt_reg[0]/C Min Period n/a FDRE/C n/a 1.000 39.725 38.725 SLICE_X111Y34 hor_cnt_reg[1]/C Min Period n/a FDRE/C n/a 1.000 39.725 38.725 SLICE_X112Y34 hor_cnt_reg[2]/C Min Period n/a FDRE/C n/a 1.000 39.725 38.725 SLICE_X112Y34 hor_cnt_reg[3]/C Min Period n/a FDRE/C n/a 1.000 39.725 38.725 SLICE_X113Y33 hor_cnt_reg[4]/C Min Period n/a FDRE/C n/a 1.000 39.725 38.725 SLICE_X113Y33 hor_cnt_reg[5]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 39.725 173.635 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X111Y33 Hsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X113Y33 hor_cnt_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X113Y33 hor_cnt_reg[5]/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X110Y33 ver_cnt_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X110Y33 ver_cnt_reg[5]/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X110Y33 ver_cnt_reg[6]/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X110Y33 ver_cnt_reg[7]/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X110Y33 ver_cnt_reg[8]/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X110Y33 ver_cnt_reg[9]/C Low Pulse Width Fast FDRE/C n/a 0.500 19.863 19.363 SLICE_X112Y33 video_sig_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X111Y33 Hsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X110Y32 Vsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X112Y34 hor_cnt_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X111Y34 hor_cnt_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X112Y34 hor_cnt_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X112Y34 hor_cnt_reg[3]/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X113Y33 hor_cnt_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X113Y33 hor_cnt_reg[5]/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X112Y32 hor_cnt_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.500 19.863 19.363 SLICE_X112Y32 hor_cnt_reg[7]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_wiz_0 To Clock: clkfbout_clk_wiz_0 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 37.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_wiz_0 Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y1 clk_converter/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 40.000 60.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT