Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Fri Oct 20 12:03:04 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_power -file clk_gen_test_power_routed.rpt -pb clk_gen_test_power_summary_routed.pb -rpx clk_gen_test_power_routed.rpx | Design : clk_gen_test | Device : xc7z020clg484-1 | Design State : routed | Grade : commercial | Process : typical | Characterization : Production ---------------------------------------------------------------------------------------------------------------------------------------------------------- Power Report Table of Contents ----------------- 1. Summary 1.1 On-Chip Components 1.2 Power Supply Summary 1.3 Confidence Level 2. Settings 2.1 Environment 2.2 Clock Constraints 3. Detailed Reports 3.1 By Hierarchy 1. Summary ---------- +--------------------------+--------+ | Total On-Chip Power (W) | 0.239 | | Dynamic (W) | 0.117 | | Device Static (W) | 0.123 | | Effective TJA (C/W) | 11.5 | | Max Ambient (C) | 82.2 | | Junction Temperature (C) | 27.8 | | Confidence Level | Medium | | Setting File | --- | | Simulation Activity File | --- | | Design Nets Matched | NA | +--------------------------+--------+ 1.1 On-Chip Components ---------------------- +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ | Clocks | <0.001 | 5 | --- | --- | | Slice Logic | <0.001 | 91 | --- | --- | | LUT as Logic | <0.001 | 34 | 53200 | 0.06 | | Register | <0.001 | 44 | 106400 | 0.04 | | Others | 0.000 | 4 | --- | --- | | Signals | <0.001 | 61 | --- | --- | | MMCM | 0.115 | 1 | 4 | 25.00 | | I/O | 0.001 | 15 | 200 | 7.50 | | Static Power | 0.123 | | | | | Total | 0.239 | | | | +----------------+-----------+----------+-----------+-----------------+ 1.2 Power Supply Summary ------------------------ +-----------+-------------+-----------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | +-----------+-------------+-----------+-------------+------------+ | Vccint | 1.000 | 0.008 | 0.001 | 0.008 | | Vccaux | 1.800 | 0.083 | 0.064 | 0.019 | | Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | | Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | | MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | | Vccpint | 1.000 | 0.017 | 0.000 | 0.017 | | Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | | Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | | Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | +-----------+-------------+-----------+-------------+------------+ 1.3 Confidence Level -------------------- +-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ | User Input Data | Confidence | Details | Action | +-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ | Design implementation state | High | Design is routed | | | Clock nodes activity | High | User specified more than 95% of clocks | | | I/O nodes activity | High | User specified more than 95% of inputs | | | Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | | Device models | High | Device models are Production | | | | | | | | Overall confidence level | Medium | | | +-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ 2. Settings ----------- 2.1 Environment --------------- +-----------------------+------------------------+ | Ambient Temp (C) | 25.0 | | ThetaJA (C/W) | 11.5 | | Airflow (LFM) | 250 | | Heat Sink | none | | ThetaSA (C/W) | 0.0 | | Board Selection | medium (10"x10") | | # of Board Layers | 8to11 (8 to 11 Layers) | | Board Temperature (C) | 25.0 | +-----------------------+------------------------+ 2.2 Clock Constraints --------------------- +--------------------+---------------------------------------+-----------------+ | Clock | Domain | Constraint (ns) | +--------------------+---------------------------------------+-----------------+ | clk_100MHz | clk_100MHz | 10.0 | | clk_out1_clk_wiz_0 | clk_converter/inst/clk_out1_clk_wiz_0 | 39.7 | | clkfbout_clk_wiz_0 | clk_converter/inst/clkfbout_clk_wiz_0 | 40.0 | +--------------------+---------------------------------------+-----------------+ 3. Detailed Reports ------------------- 3.1 By Hierarchy ---------------- +-----------------+-----------+ | Name | Power (W) | +-----------------+-----------+ | clk_gen_test | 0.117 | | clk_converter | 0.115 | | inst | 0.115 | +-----------------+-----------+