Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
| Date         : Fri Oct 20 12:02:47 2017
| Host         : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_control_sets -verbose -file clk_gen_test_control_sets_placed.rpt
| Design       : clk_gen_test
| Device       : xc7z020
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |     5 |
| Unused register locations in slices containing registers |    28 |
+----------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              20 |            5 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              12 |            3 |
| Yes          | No                    | No                     |              10 |            2 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |               2 |            2 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+------------------------------+---------------+-----------------------+------------------+----------------+
|         Clock Signal         | Enable Signal |    Set/Reset Signal   | Slice Load Count | Bel Load Count |
+------------------------------+---------------+-----------------------+------------------+----------------+
|  clk_converter/inst/clk_out1 | Vsync_sig     | Vsync_sig_i_1_n_0     |                1 |              1 |
|  clk_converter/inst/clk_out1 | Hsync_sig     | Hsync_sig_i_1_n_0     |                1 |              1 |
|  clk_converter/inst/clk_out1 | ver_cnt       |                       |                2 |             10 |
|  clk_converter/inst/clk_out1 |               | video_sig[11]_i_1_n_0 |                3 |             12 |
|  clk_converter/inst/clk_out1 |               |                       |                5 |             20 |
+------------------------------+---------------+-----------------------+------------------+----------------+


+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 1      |                     2 |
| 10     |                     1 |
| 12     |                     1 |
| 16+    |                     1 |
+--------+-----------------------+