Folder Path

/7-szemeszter/FPGA/vga/vga.runs/impl_1/

1 directory 53 files 5.0 MiB total
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Name
Size Modified
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.Xil/ —
.init_design.begin.rst
162 B
.init_design.end.rst
0 B
.opt_design.begin.rst
162 B
.opt_design.end.rst
0 B
.place_design.begin.rst
162 B
.place_design.end.rst
0 B
.route_design.begin.rst
162 B
.route_design.end.rst
0 B
.vivado.begin.rst
157 B
.vivado.end.rst
0 B
.Vivado_Implementation.queue.rst
0 B
.write_bitstream.begin.rst
162 B
.write_bitstream.end.rst
0 B
clk_gen_test.bit
3.9 MiB
clk_gen_test.tcl
5.7 KiB
clk_gen_test.vdi
24 KiB
clk_gen_test_clock_utilization_routed.rpt
15 KiB
clk_gen_test_control_sets_placed.rpt
3.4 KiB
clk_gen_test_drc_opted.rpt
1.4 KiB
clk_gen_test_drc_routed.pb
37 B
clk_gen_test_drc_routed.rpt
1.5 KiB
clk_gen_test_drc_routed.rpx
355 B
clk_gen_test_io_placed.rpt
117 KiB
clk_gen_test_methodology_drc_routed.rpt
3.7 KiB
clk_gen_test_methodology_drc_routed.rpx
4.4 KiB
clk_gen_test_opt.dcp
218 KiB
clk_gen_test_placed.dcp
230 KiB
clk_gen_test_power_routed.rpt
7.9 KiB
clk_gen_test_power_routed.rpx
29 KiB
clk_gen_test_power_summary_routed.pb
711 B
clk_gen_test_route_status.pb
43 B
clk_gen_test_route_status.rpt
588 B
clk_gen_test_routed.dcp
238 KiB
clk_gen_test_timing_summary_routed.rpt
109 KiB
clk_gen_test_timing_summary_routed.rpx
87 KiB
clk_gen_test_utilization_placed.pb
224 B
clk_gen_test_utilization_placed.rpt
8.5 KiB
gen_run.xml
5.6 KiB
htr.txt
386 B
init_design.pb
4.5 KiB
ISEWrap.js
7.1 KiB
ISEWrap.sh
1.6 KiB
opt_design.pb
6.1 KiB
place_design.pb
13 KiB
project.wdf
3.7 KiB
route_design.pb
14 KiB
rundef.js
1.5 KiB
runme.bat
257 B
runme.log
24 KiB
runme.sh
1.0 KiB
vivado.jou
660 B
vivado.pb
149 B
write_bitstream.pb
2.5 KiB