Folder Path

/7-szemeszter/FPGA/std_adder/std_adder.sim/sim_1/behav/

2 directories 17 files 14 KiB total

	Name	Size	Modified
	Up
	.Xil/	—	05/17/2022 08:09:34 PM +00:00
	xsim.dir/	—	05/17/2022 08:12:50 PM +00:00
	compile.log	386 B	05/17/2022 08:12:50 PM +00:00
	compile.sh	270 B	05/17/2022 08:12:50 PM +00:00
	elaborate.log	865 B	05/17/2022 08:12:50 PM +00:00
	elaborate.sh	332 B	05/17/2022 08:12:50 PM +00:00
	simulate.log	48 B	05/17/2022 08:12:50 PM +00:00
	simulate.sh	262 B	05/17/2022 08:12:50 PM +00:00
	std_adder_tb.tcl	449 B	05/17/2022 08:12:50 PM +00:00
	std_adder_tb_behav.wdb	4.0 KiB	05/17/2022 08:12:50 PM +00:00
	std_adder_tb_vhdl.prj	220 B	05/17/2022 08:12:50 PM +00:00
	webtalk.jou	854 B	05/17/2022 08:12:50 PM +00:00
	webtalk.log	1.2 KiB	05/17/2022 08:12:50 PM +00:00
	webtalk_5156.backup.jou	854 B	05/17/2022 08:12:49 PM +00:00
	webtalk_5156.backup.log	1.2 KiB	05/17/2022 08:12:49 PM +00:00
	xelab.pb	1.8 KiB	05/17/2022 08:12:49 PM +00:00
	xsim.ini	39 B	05/17/2022 08:12:49 PM +00:00
	xvhdl.log	386 B	05/17/2022 08:12:49 PM +00:00
	xvhdl.pb	636 B	05/17/2022 08:12:49 PM +00:00