Folder Path

/7-szemeszter/FPGA/myand2/myand2.sim/sim_1/behav/

2 directories 17 files 13 KiB total

	Name	Size	Modified
	Up
	.Xil/	—	05/17/2022 08:09:45 PM +00:00
	xsim.dir/	—	05/17/2022 08:12:54 PM +00:00
	compile.log	342 B	05/17/2022 08:12:53 PM +00:00
	compile.sh	264 B	05/17/2022 08:12:53 PM +00:00
	elaborate.log	812 B	05/17/2022 08:12:54 PM +00:00
	elaborate.sh	326 B	05/17/2022 08:12:53 PM +00:00
	myadd2_tb.tcl	449 B	05/17/2022 08:12:53 PM +00:00
	myadd2_tb_behav.wdb	3.5 KiB	05/17/2022 08:12:53 PM +00:00
	myadd2_tb_vhdl.prj	208 B	05/17/2022 08:12:53 PM +00:00
	simulate.log	48 B	05/17/2022 08:12:53 PM +00:00
	simulate.sh	253 B	05/17/2022 08:12:53 PM +00:00
	webtalk.jou	768 B	05/17/2022 08:12:53 PM +00:00
	webtalk.log	1.1 KiB	05/17/2022 08:12:53 PM +00:00
	webtalk_4536.backup.jou	768 B	05/17/2022 08:12:53 PM +00:00
	webtalk_4536.backup.log	1.1 KiB	05/17/2022 08:12:53 PM +00:00
	xelab.pb	1.7 KiB	05/17/2022 08:12:53 PM +00:00
	xsim.ini	39 B	05/17/2022 08:12:53 PM +00:00
	xvhdl.log	342 B	05/17/2022 08:12:53 PM +00:00
	xvhdl.pb	592 B	05/17/2022 08:12:53 PM +00:00