Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
| Date         : Fri Sep 15 11:48:21 2017
| Host         : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_methodology -file myand2_methodology_drc_routed.rpt -rpx myand2_methodology_drc_routed.rpx
| Design       : myand2
| Device       : xc7z020clg484-1
| Speed File   : -1
| Design State : Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: checkpoint_myand2
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+

2. REPORT DETAILS
-----------------