Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Fri Sep 15 11:48:22 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_clock_utilization -file myand2_clock_utilization_routed.rpt | Design : myand2 | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------ Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions: Key Resource Utilization 5. Clock Regions : Global Clock Summary 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 0 | 32 | 0 | 0 | 0 | | BUFH | 0 | 72 | 0 | 0 | 0 | | BUFIO | 0 | 16 | 0 | 0 | 0 | | BUFMR | 0 | 8 | 0 | 0 | 0 | | BUFR | 0 | 16 | 0 | 0 | 0 | | MMCM | 0 | 4 | 0 | 0 | 0 | | PLL | 0 | 4 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 1000 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | | X0Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Global Clock Summary --------------------------------------- +----+----+----+ | | X0 | X1 | +----+----+----+ | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+----+ # Location of IO Primitives which is load of clock spine # Location of clock ports