Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Mon Dec 11 13:26:42 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_timing_summary -warn_on_violation -max_paths 10 -file chars_timing_summary_routed.rpt -rpx chars_timing_summary_routed.rpx | Design : chars | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 --------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 36 register/latch pins with no clock driven by root clock pin: clk_100MHz (HIGH) There are 104 register/latch pins with no clock driven by root clock pin: PmodJSTK_Int/SerialClock/CLKOUT_reg/Q (HIGH) 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 238 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 16 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 35.758 0.000 0 74 0.229 0.000 0 74 3.000 0.000 0 47 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk_converter/inst/clk_in {0.000 5.000} 10.000 100.000 clk_out_clk_100MHz_to_25MHz {0.000 20.000} 40.000 25.000 clkfbout_clk_100MHz_to_25MHz {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk_converter/inst/clk_in 3.000 0.000 0 1 clk_out_clk_100MHz_to_25MHz 35.758 0.000 0 74 0.229 0.000 0 74 19.500 0.000 0 43 clkfbout_clk_100MHz_to_25MHz 7.845 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk_converter/inst/clk_in To Clock: clk_converter/inst/clk_in Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_converter/inst/clk_in Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_converter/inst/clk_in } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out_clk_100MHz_to_25MHz To Clock: clk_out_clk_100MHz_to_25MHz Setup : 0 Failing Endpoints, Worst Slack 35.758ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.229ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 35.758ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.589ns (logic 0.934ns (26.026%) route 2.655ns (73.974%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.692ns = ( 41.692 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.917 5.468 video_sig[11]_i_1_n_0 SLICE_X112Y33 FDRE r video_sig_reg[11]_lopt_replica/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.692 41.692 clk_25MHz SLICE_X112Y33 FDRE r video_sig_reg[11]_lopt_replica/C clock pessimism 0.155 41.847 clock uncertainty -0.098 41.749 SLICE_X112Y33 FDRE (Setup_fdre_C_R) -0.524 41.225 video_sig_reg[11]_lopt_replica ------------------------------------------------------------------- required time 41.225 arrival time -5.468 ------------------------------------------------------------------- slack 35.758 Slack (MET) : 35.758ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_10/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.589ns (logic 0.934ns (26.026%) route 2.655ns (73.974%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.692ns = ( 41.692 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.917 5.468 video_sig[11]_i_1_n_0 SLICE_X112Y33 FDRE r video_sig_reg[11]_lopt_replica_10/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.692 41.692 clk_25MHz SLICE_X112Y33 FDRE r video_sig_reg[11]_lopt_replica_10/C clock pessimism 0.155 41.847 clock uncertainty -0.098 41.749 SLICE_X112Y33 FDRE (Setup_fdre_C_R) -0.524 41.225 video_sig_reg[11]_lopt_replica_10 ------------------------------------------------------------------- required time 41.225 arrival time -5.468 ------------------------------------------------------------------- slack 35.758 Slack (MET) : 35.853ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_4/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.589ns (logic 0.934ns (26.026%) route 2.655ns (73.974%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.692ns = ( 41.692 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.917 5.468 video_sig[11]_i_1_n_0 SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_4/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.692 41.692 clk_25MHz SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_4/C clock pessimism 0.155 41.847 clock uncertainty -0.098 41.749 SLICE_X113Y33 FDRE (Setup_fdre_C_R) -0.429 41.320 video_sig_reg[11]_lopt_replica_4 ------------------------------------------------------------------- required time 41.320 arrival time -5.468 ------------------------------------------------------------------- slack 35.853 Slack (MET) : 35.853ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_5/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.589ns (logic 0.934ns (26.026%) route 2.655ns (73.974%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.692ns = ( 41.692 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.917 5.468 video_sig[11]_i_1_n_0 SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_5/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.692 41.692 clk_25MHz SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_5/C clock pessimism 0.155 41.847 clock uncertainty -0.098 41.749 SLICE_X113Y33 FDRE (Setup_fdre_C_R) -0.429 41.320 video_sig_reg[11]_lopt_replica_5 ------------------------------------------------------------------- required time 41.320 arrival time -5.468 ------------------------------------------------------------------- slack 35.853 Slack (MET) : 35.853ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_6/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.589ns (logic 0.934ns (26.026%) route 2.655ns (73.974%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.692ns = ( 41.692 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.917 5.468 video_sig[11]_i_1_n_0 SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_6/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.692 41.692 clk_25MHz SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_6/C clock pessimism 0.155 41.847 clock uncertainty -0.098 41.749 SLICE_X113Y33 FDRE (Setup_fdre_C_R) -0.429 41.320 video_sig_reg[11]_lopt_replica_6 ------------------------------------------------------------------- required time 41.320 arrival time -5.468 ------------------------------------------------------------------- slack 35.853 Slack (MET) : 35.853ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_9/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.589ns (logic 0.934ns (26.026%) route 2.655ns (73.974%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.032ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.692ns = ( 41.692 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.917 5.468 video_sig[11]_i_1_n_0 SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_9/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.692 41.692 clk_25MHz SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_9/C clock pessimism 0.155 41.847 clock uncertainty -0.098 41.749 SLICE_X113Y33 FDRE (Setup_fdre_C_R) -0.429 41.320 video_sig_reg[11]_lopt_replica_9 ------------------------------------------------------------------- required time 41.320 arrival time -5.468 ------------------------------------------------------------------- slack 35.853 Slack (MET) : 36.004ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_7/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.439ns (logic 0.934ns (27.157%) route 2.505ns (72.843%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.030ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.694ns = ( 41.694 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.767 5.318 video_sig[11]_i_1_n_0 SLICE_X113Y35 FDRE r video_sig_reg[11]_lopt_replica_7/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.694 41.694 clk_25MHz SLICE_X113Y35 FDRE r video_sig_reg[11]_lopt_replica_7/C clock pessimism 0.155 41.849 clock uncertainty -0.098 41.751 SLICE_X113Y35 FDRE (Setup_fdre_C_R) -0.429 41.322 video_sig_reg[11]_lopt_replica_7 ------------------------------------------------------------------- required time 41.322 arrival time -5.318 ------------------------------------------------------------------- slack 36.004 Slack (MET) : 36.004ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_8/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.439ns (logic 0.934ns (27.157%) route 2.505ns (72.843%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.030ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.694ns = ( 41.694 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.767 5.318 video_sig[11]_i_1_n_0 SLICE_X113Y35 FDRE r video_sig_reg[11]_lopt_replica_8/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.694 41.694 clk_25MHz SLICE_X113Y35 FDRE r video_sig_reg[11]_lopt_replica_8/C clock pessimism 0.155 41.849 clock uncertainty -0.098 41.751 SLICE_X113Y35 FDRE (Setup_fdre_C_R) -0.429 41.322 video_sig_reg[11]_lopt_replica_8 ------------------------------------------------------------------- required time 41.322 arrival time -5.318 ------------------------------------------------------------------- slack 36.004 Slack (MET) : 36.065ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.381ns (logic 0.934ns (27.625%) route 2.447ns (72.375%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.027ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.697ns = ( 41.697 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.709 5.260 video_sig[11]_i_1_n_0 SLICE_X113Y39 FDRE r video_sig_reg[11]/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.697 41.697 clk_25MHz SLICE_X113Y39 FDRE r video_sig_reg[11]/C clock pessimism 0.155 41.852 clock uncertainty -0.098 41.754 SLICE_X113Y39 FDRE (Setup_fdre_C_R) -0.429 41.325 video_sig_reg[11] ------------------------------------------------------------------- required time 41.325 arrival time -5.260 ------------------------------------------------------------------- slack 36.065 Slack (MET) : 36.065ns (required time - arrival time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_11/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.381ns (logic 0.934ns (27.625%) route 2.447ns (72.375%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.027ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.697ns = ( 41.697 - 40.000 ) Source Clock Delay (SCD): 1.879ns Clock Pessimism Removal (CPR): 0.155ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.803 1.803 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.793 -1.990 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.889 -0.101 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.879 1.879 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.456 2.335 r ver_cnt_reg[9]/Q net (fo=5, routed) 1.290 3.625 ver_cnt_reg_n_0_[9] SLICE_X113Y43 LUT4 (Prop_lut4_I1_O) 0.152 3.777 r out_reg[6]_i_5/O net (fo=2, routed) 0.448 4.225 out_reg[6]_i_5_n_0 SLICE_X113Y43 LUT6 (Prop_lut6_I5_O) 0.326 4.551 r video_sig[11]_i_1/O net (fo=12, routed) 0.709 5.260 video_sig[11]_i_1_n_0 SLICE_X113Y39 FDRE r video_sig_reg[11]_lopt_replica_11/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r BUFGCTRL_X0Y2 BUFG 0.000 40.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 1.609 41.609 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.425 38.184 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.725 39.909 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 40.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.697 41.697 clk_25MHz SLICE_X113Y39 FDRE r video_sig_reg[11]_lopt_replica_11/C clock pessimism 0.155 41.852 clock uncertainty -0.098 41.754 SLICE_X113Y39 FDRE (Setup_fdre_C_R) -0.429 41.325 video_sig_reg[11]_lopt_replica_11 ------------------------------------------------------------------- required time 41.325 arrival time -5.260 ------------------------------------------------------------------- slack 36.065 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.229ns (arrival time - required time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.366ns (logic 0.186ns (50.765%) route 0.180ns (49.235%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.911ns Source Clock Delay (SCD): 0.640ns Clock Pessimism Removal (CPR): 0.255ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.640 0.640 clk_25MHz SLICE_X110Y44 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y44 FDRE (Prop_fdre_C_Q) 0.141 0.781 r ver_cnt_reg[1]/Q net (fo=17, routed) 0.180 0.961 ver_cnt_reg_n_0_[1] SLICE_X112Y44 LUT6 (Prop_lut6_I2_O) 0.045 1.006 r ver_cnt[5]_i_1/O net (fo=1, routed) 0.000 1.006 ver_cnt[5]_i_1_n_0 SLICE_X112Y44 FDRE r ver_cnt_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.911 0.911 clk_25MHz SLICE_X112Y44 FDRE r ver_cnt_reg[5]/C clock pessimism -0.255 0.656 SLICE_X112Y44 FDRE (Hold_fdre_C_D) 0.121 0.777 ver_cnt_reg[5] ------------------------------------------------------------------- required time -0.777 arrival time 1.006 ------------------------------------------------------------------- slack 0.229 Slack (MET) : 0.230ns (arrival time - required time) Source: hor_cnt_reg[5]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.338ns (logic 0.186ns (55.040%) route 0.152ns (44.960%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.910ns Source Clock Delay (SCD): 0.639ns Clock Pessimism Removal (CPR): 0.255ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.639 0.639 clk_25MHz SLICE_X113Y42 FDRE r hor_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y42 FDRE (Prop_fdre_C_Q) 0.141 0.780 r hor_cnt_reg[5]/Q net (fo=14, routed) 0.152 0.932 current_digit[2] SLICE_X111Y42 LUT6 (Prop_lut6_I1_O) 0.045 0.977 r hor_cnt[7]_i_1/O net (fo=1, routed) 0.000 0.977 hor_cnt[7] SLICE_X111Y42 FDRE r hor_cnt_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.910 0.910 clk_25MHz SLICE_X111Y42 FDRE r hor_cnt_reg[7]/C clock pessimism -0.255 0.655 SLICE_X111Y42 FDRE (Hold_fdre_C_D) 0.092 0.747 hor_cnt_reg[7] ------------------------------------------------------------------- required time -0.747 arrival time 0.977 ------------------------------------------------------------------- slack 0.230 Slack (MET) : 0.233ns (arrival time - required time) Source: hor_cnt_reg[5]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[6]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.341ns (logic 0.186ns (54.555%) route 0.155ns (45.445%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.910ns Source Clock Delay (SCD): 0.639ns Clock Pessimism Removal (CPR): 0.255ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.639 0.639 clk_25MHz SLICE_X113Y42 FDRE r hor_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y42 FDRE (Prop_fdre_C_Q) 0.141 0.780 r hor_cnt_reg[5]/Q net (fo=14, routed) 0.155 0.935 current_digit[2] SLICE_X111Y42 LUT5 (Prop_lut5_I1_O) 0.045 0.980 r hor_cnt[6]_i_1/O net (fo=1, routed) 0.000 0.980 hor_cnt[6]_i_1_n_0 SLICE_X111Y42 FDRE r hor_cnt_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.910 0.910 clk_25MHz SLICE_X111Y42 FDRE r hor_cnt_reg[6]/C clock pessimism -0.255 0.655 SLICE_X111Y42 FDRE (Hold_fdre_C_D) 0.092 0.747 hor_cnt_reg[6] ------------------------------------------------------------------- required time -0.747 arrival time 0.980 ------------------------------------------------------------------- slack 0.233 Slack (MET) : 0.235ns (arrival time - required time) Source: hor_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.357ns (logic 0.189ns (52.913%) route 0.168ns (47.087%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.911ns Source Clock Delay (SCD): 0.639ns Clock Pessimism Removal (CPR): 0.255ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.639 0.639 clk_25MHz SLICE_X111Y42 FDRE r hor_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y42 FDRE (Prop_fdre_C_Q) 0.141 0.780 r hor_cnt_reg[0]/Q net (fo=10, routed) 0.168 0.948 hor_cnt_reg_n_0_[0] SLICE_X111Y43 LUT4 (Prop_lut4_I3_O) 0.048 0.996 r hor_cnt[3]_i_1/O net (fo=1, routed) 0.000 0.996 hor_cnt[3] SLICE_X111Y43 FDRE r hor_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.911 0.911 clk_25MHz SLICE_X111Y43 FDRE r hor_cnt_reg[3]/C clock pessimism -0.255 0.656 SLICE_X111Y43 FDRE (Hold_fdre_C_D) 0.105 0.761 hor_cnt_reg[3] ------------------------------------------------------------------- required time -0.761 arrival time 0.996 ------------------------------------------------------------------- slack 0.235 Slack (MET) : 0.244ns (arrival time - required time) Source: hor_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.351ns (logic 0.183ns (52.101%) route 0.168ns (47.899%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.910ns Source Clock Delay (SCD): 0.639ns Clock Pessimism Removal (CPR): 0.271ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.639 0.639 clk_25MHz SLICE_X111Y42 FDRE r hor_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y42 FDRE (Prop_fdre_C_Q) 0.141 0.780 r hor_cnt_reg[0]/Q net (fo=10, routed) 0.168 0.948 hor_cnt_reg_n_0_[0] SLICE_X111Y42 LUT2 (Prop_lut2_I0_O) 0.042 0.990 r hor_cnt[1]_i_1/O net (fo=1, routed) 0.000 0.990 hor_cnt[1] SLICE_X111Y42 FDRE r hor_cnt_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.910 0.910 clk_25MHz SLICE_X111Y42 FDRE r hor_cnt_reg[1]/C clock pessimism -0.271 0.639 SLICE_X111Y42 FDRE (Hold_fdre_C_D) 0.107 0.746 hor_cnt_reg[1] ------------------------------------------------------------------- required time -0.746 arrival time 0.990 ------------------------------------------------------------------- slack 0.244 Slack (MET) : 0.245ns (arrival time - required time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.350ns (logic 0.189ns (53.937%) route 0.161ns (46.063%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.911ns Source Clock Delay (SCD): 0.640ns Clock Pessimism Removal (CPR): 0.271ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.640 0.640 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.141 0.781 f ver_cnt_reg[9]/Q net (fo=5, routed) 0.161 0.942 ver_cnt_reg_n_0_[9] SLICE_X113Y45 LUT5 (Prop_lut5_I3_O) 0.048 0.990 r ver_cnt[0]_i_1/O net (fo=1, routed) 0.000 0.990 ver_cnt[0]_i_1_n_0 SLICE_X113Y45 FDRE r ver_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.911 0.911 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[0]/C clock pessimism -0.271 0.640 SLICE_X113Y45 FDRE (Hold_fdre_C_D) 0.105 0.745 ver_cnt_reg[0] ------------------------------------------------------------------- required time -0.745 arrival time 0.990 ------------------------------------------------------------------- slack 0.245 Slack (MET) : 0.253ns (arrival time - required time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.345ns (logic 0.186ns (53.876%) route 0.159ns (46.124%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.911ns Source Clock Delay (SCD): 0.640ns Clock Pessimism Removal (CPR): 0.271ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.640 0.640 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y45 FDRE (Prop_fdre_C_Q) 0.141 0.781 r ver_cnt_reg[0]/Q net (fo=18, routed) 0.159 0.940 ver_cnt_reg_n_0_[0] SLICE_X113Y45 LUT6 (Prop_lut6_I3_O) 0.045 0.985 r ver_cnt[9]_i_2/O net (fo=1, routed) 0.000 0.985 ver_cnt[9]_i_2_n_0 SLICE_X113Y45 FDRE r ver_cnt_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.911 0.911 clk_25MHz SLICE_X113Y45 FDRE r ver_cnt_reg[9]/C clock pessimism -0.271 0.640 SLICE_X113Y45 FDRE (Hold_fdre_C_D) 0.092 0.732 ver_cnt_reg[9] ------------------------------------------------------------------- required time -0.732 arrival time 0.985 ------------------------------------------------------------------- slack 0.253 Slack (MET) : 0.256ns (arrival time - required time) Source: out_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.340ns (logic 0.141ns (41.516%) route 0.199ns (58.484%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.909ns Source Clock Delay (SCD): 0.640ns Clock Pessimism Removal (CPR): 0.255ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.640 0.640 clk_25MHz SLICE_X111Y44 FDRE r out_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y44 FDRE (Prop_fdre_C_Q) 0.141 0.781 r out_reg_reg[0]/Q net (fo=12, routed) 0.199 0.979 out_reg_reg_n_0_[0] SLICE_X113Y39 FDRE r video_sig_reg[11]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.909 0.909 clk_25MHz SLICE_X113Y39 FDRE r video_sig_reg[11]/C clock pessimism -0.255 0.654 SLICE_X113Y39 FDRE (Hold_fdre_C_D) 0.070 0.724 video_sig_reg[11] ------------------------------------------------------------------- required time -0.724 arrival time 0.979 ------------------------------------------------------------------- slack 0.256 Slack (MET) : 0.263ns (arrival time - required time) Source: hor_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.354ns (logic 0.186ns (52.507%) route 0.168ns (47.493%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.910ns Source Clock Delay (SCD): 0.639ns Clock Pessimism Removal (CPR): 0.271ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.639 0.639 clk_25MHz SLICE_X111Y42 FDRE r hor_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y42 FDRE (Prop_fdre_C_Q) 0.141 0.780 f hor_cnt_reg[0]/Q net (fo=10, routed) 0.168 0.948 hor_cnt_reg_n_0_[0] SLICE_X111Y42 LUT1 (Prop_lut1_I0_O) 0.045 0.993 r hor_cnt[0]_i_1/O net (fo=1, routed) 0.000 0.993 hor_cnt[0] SLICE_X111Y42 FDRE r hor_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.910 0.910 clk_25MHz SLICE_X111Y42 FDRE r hor_cnt_reg[0]/C clock pessimism -0.271 0.639 SLICE_X111Y42 FDRE (Hold_fdre_C_D) 0.091 0.730 hor_cnt_reg[0] ------------------------------------------------------------------- required time -0.730 arrival time 0.993 ------------------------------------------------------------------- slack 0.263 Slack (MET) : 0.277ns (arrival time - required time) Source: hor_cnt_reg[5]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.368ns (logic 0.186ns (50.580%) route 0.182ns (49.420%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.910ns Source Clock Delay (SCD): 0.639ns Clock Pessimism Removal (CPR): 0.271ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.595 0.595 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.150 -0.555 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.529 -0.026 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.639 0.639 clk_25MHz SLICE_X113Y42 FDRE r hor_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y42 FDRE (Prop_fdre_C_Q) 0.141 0.780 r hor_cnt_reg[5]/Q net (fo=14, routed) 0.182 0.961 current_digit[2] SLICE_X113Y42 LUT6 (Prop_lut6_I0_O) 0.045 1.006 r hor_cnt[5]_i_1/O net (fo=1, routed) 0.000 1.006 hor_cnt[5] SLICE_X113Y42 FDRE r hor_cnt_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r BUFGCTRL_X0Y2 BUFG 0.000 0.000 r clk_100MHz_IBUF_BUFG_inst/O net (fo=37, routed) 0.862 0.862 clk_converter/inst/clk_in MMCME2_ADV_X1Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.467 -0.605 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.576 -0.029 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -0.000 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.910 0.910 clk_25MHz SLICE_X113Y42 FDRE r hor_cnt_reg[5]/C clock pessimism -0.271 0.639 SLICE_X113Y42 FDRE (Hold_fdre_C_D) 0.091 0.730 hor_cnt_reg[5] ------------------------------------------------------------------- required time -0.730 arrival time 1.006 ------------------------------------------------------------------- slack 0.277 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out_clk_100MHz_to_25MHz Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y1 clk_converter/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X112Y41 Hsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X113Y44 Vsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y42 hor_cnt_reg[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y42 hor_cnt_reg[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y42 hor_cnt_reg[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y44 out_reg_reg[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y44 out_reg_reg[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y44 out_reg_reg[3]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y35 video_sig_reg[11]_lopt_replica_7/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y35 video_sig_reg[11]_lopt_replica_8/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y44 Vsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y44 out_reg_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y44 out_reg_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y44 out_reg_reg[3]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y43 out_reg_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y43 out_reg_reg[5]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y43 out_reg_reg[6]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y44 ver_cnt_reg[5]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y41 Hsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y44 Vsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y42 hor_cnt_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y42 hor_cnt_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y42 hor_cnt_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y44 out_reg_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y44 out_reg_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y44 out_reg_reg[3]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y43 out_reg_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y43 out_reg_reg[5]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_100MHz_to_25MHz To Clock: clkfbout_clk_100MHz_to_25MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_100MHz_to_25MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y3 clk_converter/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT