Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
| Date         : Mon Dec 11 13:26:24 2017
| Host         : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_control_sets -verbose -file chars_control_sets_placed.rpt
| Design       : chars
| Device       : xc7z020
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |    12 |
| Unused register locations in slices containing registers |    43 |
+----------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              52 |           17 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              22 |            8 |
| Yes          | No                    | No                     |             105 |           30 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |               2 |            2 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+-----------------------------+-----------------------------------------+-------------------------------+------------------+----------------+
|         Clock Signal        |              Enable Signal              |        Set/Reset Signal       | Slice Load Count | Bel Load Count |
+-----------------------------+-----------------------------------------+-------------------------------+------------------+----------------+
|  clk_converter/inst/clk_out | Vsync_sig                               | Vsync_sig_i_1_n_0             |                1 |              1 |
|  clk_converter/inst/clk_out | Hsync_sig                               | Hsync_sig_i_1_n_0             |                1 |              1 |
|  clk_converter/inst/clk_out | out_reg[6]_i_1_n_0                      |                               |                2 |              7 |
|  CLKOUT                     | PmodJSTK_Int/SPI_Int/rSR[7]_i_1_n_0     |                               |                1 |              8 |
|  clk_100MHz_IBUF_BUFG       |                                         | PmodJSTK_Int/SerialClock/load |                3 |             10 |
|  clk_converter/inst/clk_out |                                         |                               |                3 |             10 |
|  clk_converter/inst/clk_out | ver_cnt[9]_i_1_n_0                      |                               |                6 |             10 |
|  clk_converter/inst/clk_out |                                         | video_sig[11]_i_1_n_0         |                5 |             12 |
| ~CLKOUT                     |                                         |                               |                6 |             16 |
|  clk_100MHz_IBUF_BUFG       |                                         |                               |                8 |             26 |
| ~CLKOUT                     | PmodJSTK_Int/SPI_Ctrl/__1/i__n_0        |                               |               10 |             40 |
| ~CLKOUT                     | PmodJSTK_Int/SPI_Ctrl/tmpSR[39]_i_1_n_0 |                               |               11 |             40 |
+-----------------------------+-----------------------------------------+-------------------------------+------------------+----------------+


+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 1      |                     2 |
| 7      |                     1 |
| 8      |                     1 |
| 10     |                     3 |
| 12     |                     1 |
| 16+    |                     4 |
+--------+-----------------------+