Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Mon Dec 11 13:26:43 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_clock_utilization -file chars_clock_utilization_routed.rpt | Design : chars | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------ Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions: Key Resource Utilization 5. Clock Regions : Global Clock Summary 6. Cell Type Counts per Global Clock: Region X1Y0 7. Load Cell Placement Summary for Global Clock g0 8. Load Cell Placement Summary for Global Clock g1 9. Load Cell Placement Summary for Global Clock g2 10. Load Cell Placement Summary for Global Clock g3 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 4 | 32 | 0 | 0 | 0 | | BUFH | 0 | 72 | 0 | 0 | 0 | | BUFIO | 0 | 16 | 0 | 0 | 0 | | BUFMR | 0 | 8 | 0 | 0 | 0 | | BUFR | 0 | 16 | 0 | 0 | 0 | | MMCM | 1 | 4 | 0 | 0 | 0 | | PLL | 0 | 4 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+------------------------------+-----------------------------------+-----------------------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Root | Clock Delay Group | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+------------------------------+-----------------------------------+-----------------------------------------------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | | | 1 | 104 | 0 | | | FSM_sequential_STATE_reg[2]_i_2/O | CLKOUT | | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | | | 1 | 41 | 0 | 40.000 | clk_out_clk_100MHz_to_25MHz | clk_converter/inst/clkout1_buf/O | clk_converter/inst/clk_out | | g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | | | 1 | 37 | 0 | | | clk_100MHz_IBUF_BUFG_inst/O | clk_100MHz_IBUF_BUFG | | g3 | src1 | BUFG/O | None | BUFGCTRL_X0Y3 | n/a | | | 1 | 1 | 0 | 10.000 | clkfbout_clk_100MHz_to_25MHz | clk_converter/inst/clkf_buf/O | clk_converter/inst/clkfbout_buf_clk_100MHz_to_25MHz | +-----------+-----------+-----------------+------------+---------------+--------------+------+-------------------+-------------------+-------------+-----------------+--------------+------------------------------+-----------------------------------+-----------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------------------+-------------------------------------------+-------------------------------------------------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------------------+-------------------------------------------+-------------------------------------------------+ | src0 | g0 | FDRE/Q | None | SLICE_X84Y38 | X1Y0 | 1 | 2 | | | PmodJSTK_Int/SerialClock/CLKOUT_reg/Q | PmodJSTK_Int/SerialClock/CLKOUT_reg_0 | | src1 | g1 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y0 | X1Y0 | 1 | 0 | 40.000 | clk_out_clk_100MHz_to_25MHz | clk_converter/inst/mmcm_adv_inst/CLKOUT0 | clk_converter/inst/clk_out_clk_100MHz_to_25MHz | | src1 | g3 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y0 | X1Y0 | 1 | 0 | 10.000 | clkfbout_clk_100MHz_to_25MHz | clk_converter/inst/mmcm_adv_inst/CLKFBOUT | clk_converter/inst/clkfbout_clk_100MHz_to_25MHz | | src2 | g2 | IBUF/O | IOB_X0Y26 | IOB_X0Y26 | X0Y0 | 1 | 0 | | | clk_100MHz_IBUF_inst/O | clk_100MHz_IBUF | +-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------------------+-------------------------------------------+-------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2500 | 0 | 1000 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y0 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 181 | 3200 | 39 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | | X0Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 40 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Global Clock Summary --------------------------------------- +----+----+----+ | | X0 | X1 | +----+----+----+ | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 4 | +----+----+----+ 6. Cell Type Counts per Global Clock: Region X1Y0 ------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------------------------------------+ | g0 | n/a | BUFG/O | None | 104 | 0 | 104 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKOUT | | g1 | n/a | BUFG/O | None | 41 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_converter/inst/clk_out | | g2 | n/a | BUFG/O | None | 37 | 0 | 36 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clk_100MHz_IBUF_BUFG | | g3 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | clk_converter/inst/clkfbout_buf_clk_100MHz_to_25MHz | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-----------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 7. Load Cell Placement Summary for Global Clock g0 -------------------------------------------------- +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ | g0 | BUFG/O | n/a | | | | | 104 | 0 | 0 | 0 | CLKOUT | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+--------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 104 | +----+----+------+ 8. Load Cell Placement Summary for Global Clock g1 -------------------------------------------------- +-----------+-----------------+-------------------+-----------------------------+-------------+----------------+----------+-------------+----------+----------------+----------+----------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------------------------+-------------+----------------+----------+-------------+----------+----------------+----------+----------------------------+ | g1 | BUFG/O | n/a | clk_out_clk_100MHz_to_25MHz | 40.000 | {0.000 20.000} | | 41 | 0 | 0 | 0 | clk_converter/inst/clk_out | +-----------+-----------------+-------------------+-----------------------------+-------------+----------------+----------+-------------+----------+----------------+----------+----------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----+ | | X0 | X1 | +----+----+-----+ | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 41 | +----+----+-----+ 9. Load Cell Placement Summary for Global Clock g2 -------------------------------------------------- +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------+ | g2 | BUFG/O | n/a | | | | | 36 | 0 | 1 | 0 | clk_100MHz_IBUF_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+----------+-------------+----------+----------------+----------+----------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----+ | | X0 | X1 | +----+----+-----+ | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 37 | +----+----+-----+ 10. Load Cell Placement Summary for Global Clock g3 --------------------------------------------------- +-----------+-----------------+-------------------+------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Root (R) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------+ | g3 | BUFG/O | n/a | clkfbout_clk_100MHz_to_25MHz | 10.000 | {0.000 5.000} | | 0 | 0 | 1 | 0 | clk_converter/inst/clkfbout_buf_clk_100MHz_to_25MHz | +-----------+-----------------+-------------------+------------------------------+-------------+---------------+----------+-------------+----------+----------------+----------+-----------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+ | | X0 | X1 | +----+----+----+ | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 1 | +----+----+----+ # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y3 [get_cells clk_converter/inst/clkf_buf] set_property LOC BUFGCTRL_X0Y1 [get_cells clk_converter/inst/clkout1_buf] set_property LOC BUFGCTRL_X0Y2 [get_cells clk_100MHz_IBUF_BUFG_inst] set_property LOC BUFGCTRL_X0Y0 [get_cells FSM_sequential_STATE_reg[2]_i_2] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X0Y26 [get_ports clk_100MHz] # Clock net "clk_converter/inst/clk_out" driven by instance "clk_converter/inst/clkout1_buf" located at site "BUFGCTRL_X0Y1" #startgroup create_pblock {CLKAG_clk_converter/inst/clk_out} add_cells_to_pblock [get_pblocks {CLKAG_clk_converter/inst/clk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_converter/inst/clk_out"}]]] resize_pblock [get_pblocks {CLKAG_clk_converter/inst/clk_out}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} #endgroup # Clock net "clk_100MHz_IBUF_BUFG" driven by instance "clk_100MHz_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y2" #startgroup create_pblock {CLKAG_clk_100MHz_IBUF_BUFG} add_cells_to_pblock [get_pblocks {CLKAG_clk_100MHz_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=clk_converter/inst/mmcm_adv_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_100MHz_IBUF_BUFG"}]]] resize_pblock [get_pblocks {CLKAG_clk_100MHz_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} #endgroup # Clock net "CLKOUT" driven by instance "FSM_sequential_STATE_reg[2]_i_2" located at site "BUFGCTRL_X0Y0" #startgroup create_pblock {CLKAG_CLKOUT} add_cells_to_pblock [get_pblocks {CLKAG_CLKOUT}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="CLKOUT"}]]] resize_pblock [get_pblocks {CLKAG_CLKOUT}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} #endgroup