#----------------------------------------------------------- # Vivado v2016.4 (64-bit) # SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016 # IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016 # Start of session at: Tue Dec 5 13:40:36 2017 # Process ID: 14620 # Current directory: /home/hakta/Documents/FPGA/display_num/chars.runs/synth_1 # Command line: vivado -log chars.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source chars.tcl # Log file: /home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/chars.vds # Journal file: /home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/vivado.jou #----------------------------------------------------------- source chars.tcl -notrace Command: synth_design -top chars -part xc7z020clg484-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14624 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1074.973 ; gain = 147.082 ; free physical = 15176 ; free virtual = 16919 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'chars' [/home/hakta/Documents/FPGA/display_num/chars.srcs/sources_1/new/chars.vhd:41] INFO: [Synth 8-3491] module 'clk_100MHz_to_25MHz' declared at '/home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/.Xil/Vivado-14620-VLSI-01/realtime/clk_100MHz_to_25MHz_stub.vhdl:5' bound to instance 'clk_converter' of component 'clk_100MHz_to_25MHz' [/home/hakta/Documents/FPGA/display_num/chars.srcs/sources_1/new/chars.vhd:164] INFO: [Synth 8-638] synthesizing module 'clk_100MHz_to_25MHz' [/home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/.Xil/Vivado-14620-VLSI-01/realtime/clk_100MHz_to_25MHz_stub.vhdl:13] INFO: [Synth 8-256] done synthesizing module 'chars' (1#1) [/home/hakta/Documents/FPGA/display_num/chars.srcs/sources_1/new/chars.vhd:41] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1115.449 ; gain = 187.559 ; free physical = 15134 ; free virtual = 16877 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1115.449 ; gain = 187.559 ; free physical = 15134 ; free virtual = 16877 --------------------------------------------------------------------------------- WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'clk_100MHz_to_25MHz' instantiated as 'clk_converter' [/home/hakta/Documents/FPGA/display_num/chars.srcs/sources_1/new/chars.vhd:164] INFO: [Device 21-403] Loading part xc7z020clg484-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/.Xil/Vivado-14620-VLSI-01/dcp/clk_100MHz_to_25MHz_in_context.xdc] for cell 'clk_converter' Finished Parsing XDC File [/home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/.Xil/Vivado-14620-VLSI-01/dcp/clk_100MHz_to_25MHz_in_context.xdc] for cell 'clk_converter' Parsing XDC File [/home/hakta/Documents/FPGA/display_num/chars.srcs/constrs_1/new/chars.xdc] WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 33]]'. [/home/hakta/Documents/FPGA/display_num/chars.srcs/constrs_1/new/chars.xdc:39] WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 34]]'. [/home/hakta/Documents/FPGA/display_num/chars.srcs/constrs_1/new/chars.xdc:44] WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 35]]'. [/home/hakta/Documents/FPGA/display_num/chars.srcs/constrs_1/new/chars.xdc:49] WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 13]]'. [/home/hakta/Documents/FPGA/display_num/chars.srcs/constrs_1/new/chars.xdc:52] Finished Parsing XDC File [/home/hakta/Documents/FPGA/display_num/chars.srcs/constrs_1/new/chars.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/hakta/Documents/FPGA/display_num/chars.srcs/constrs_1/new/chars.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/chars_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/chars_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.777 ; gain = 0.004 ; free physical = 14932 ; free virtual = 16675 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1462.777 ; gain = 534.887 ; free physical = 14928 ; free virtual = 16670 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1462.777 ; gain = 534.887 ; free physical = 14928 ; free virtual = 16670 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property IO_BUFFER_TYPE = NONE for clk_100MHz. (constraint file /home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/.Xil/Vivado-14620-VLSI-01/dcp/clk_100MHz_to_25MHz_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for clk_100MHz. (constraint file /home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/.Xil/Vivado-14620-VLSI-01/dcp/clk_100MHz_to_25MHz_in_context.xdc, line 4). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1462.777 ; gain = 534.887 ; free physical = 14928 ; free virtual = 16670 --------------------------------------------------------------------------------- INFO: [Synth 8-5546] ROM "ver_cnt" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "out_reg" won't be mapped to RAM because it is too sparse --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1462.777 ; gain = 534.887 ; free physical = 14907 ; free virtual = 16649 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 2 +---Registers : 12 Bit Registers := 1 10 Bit Registers := 2 8 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 3 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 1 Bit Muxes := 5 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module chars Detailed RTL Component Info : +---Adders : 2 Input 10 Bit Adders := 2 +---Registers : 12 Bit Registers := 1 10 Bit Registers := 2 8 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 3 Input 8 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 1 Bit Muxes := 5 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ver_cnt" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-3333] propagating constant 0 across sequential element (\out_reg_reg[7] ) INFO: [Synth 8-3886] merging instance 'video_sig_reg[0]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[1]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[2]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[3]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[4]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[5]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[6]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[7]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[8]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[9]' (FDR) to 'video_sig_reg[11]' INFO: [Synth 8-3886] merging instance 'video_sig_reg[10]' (FDR) to 'video_sig_reg[11]' WARNING: [Synth 8-3332] Sequential element (out_reg_reg[7]) is unused and will be removed from module chars. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14900 ; free virtual = 16641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: +------------+-----------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+-----------------+---------------+----------------+ |chars | font_rom_hex[0] | 128x7 | LUT | |chars | font_rom_hex[0] | 64x7 | LUT | |chars | font_rom_hex[0] | 128x7 | LUT | |chars | font_rom_hex[0] | 64x7 | LUT | +------------+-----------------+---------------+----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- INFO: [Synth 8-5578] Moved timing constraint from pin 'clk_converter/clk_out' to pin 'clk_converter/bbstub_clk_out/O' INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14891 ; free virtual = 16618 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14880 ; free virtual = 16607 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16599 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16598 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16598 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16598 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16598 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16598 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16598 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+--------------------+----------+ | |BlackBox name |Instances | +------+--------------------+----------+ |1 |clk_100MHz_to_25MHz | 1| +------+--------------------+----------+ Report Cell Usage: +------+-------------------------+------+ | |Cell |Count | +------+-------------------------+------+ |1 |clk_100MHz_to_25MHz_bbox | 1| |2 |LUT1 | 1| |3 |LUT2 | 5| |4 |LUT3 | 11| |5 |LUT4 | 6| |6 |LUT5 | 14| |7 |LUT6 | 19| |8 |FDRE | 30| |9 |OBUF | 14| +------+-------------------------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 101| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16598 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1462.781 ; gain = 107.477 ; free physical = 14871 ; free virtual = 16598 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 1462.781 ; gain = 534.891 ; free physical = 14871 ; free virtual = 16598 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 40 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1462.781 ; gain = 467.387 ; free physical = 14872 ; free virtual = 16599 INFO: [Common 17-1381] The checkpoint '/home/hakta/Documents/FPGA/display_num/chars.runs/synth_1/chars.dcp' has been generated. report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1486.789 ; gain = 0.000 ; free physical = 14870 ; free virtual = 16597 INFO: [Common 17-206] Exiting Vivado at Tue Dec 5 13:41:07 2017...