Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Tue Dec 5 13:41:48 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_timing_summary -warn_on_violation -max_paths 10 -file chars_timing_summary_routed.rpt -rpx chars_timing_summary_routed.rpx | Design : chars | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 --------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 0 input ports with no input delay specified. There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 14 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 35.650 0.000 0 74 0.174 0.000 0 74 3.000 0.000 0 47 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk_100MHz {0.000 5.000} 10.000 100.000 clk_out_clk_100MHz_to_25MHz {0.000 20.000} 40.000 25.000 clkfbout_clk_100MHz_to_25MHz {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk_100MHz 3.000 0.000 0 1 clk_out_clk_100MHz_to_25MHz 35.650 0.000 0 74 0.174 0.000 0 74 19.500 0.000 0 43 clkfbout_clk_100MHz_to_25MHz 7.845 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk_100MHz To Clock: clk_100MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100MHz } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out_clk_100MHz_to_25MHz To Clock: clk_out_clk_100MHz_to_25MHz Setup : 0 Failing Endpoints, Worst Slack 35.650ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.174ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 35.650ns (required time - arrival time) Source: hor_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: Hsync_sig_reg/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.801ns (logic 1.073ns (28.227%) route 2.728ns (71.773%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.381ns = ( 38.619 - 40.000 ) Source Clock Delay (SCD): -0.741ns Clock Pessimism Removal (CPR): 0.619ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.871 -0.741 clk_25MHz SLICE_X111Y33 FDRE r hor_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y33 FDRE (Prop_fdre_C_Q) 0.419 -0.322 r hor_cnt_reg[7]/Q net (fo=10, routed) 1.520 1.199 current_digit[4] SLICE_X110Y33 LUT4 (Prop_lut4_I3_O) 0.327 1.526 r Hsync_sig_i_3/O net (fo=1, routed) 0.674 2.200 Hsync_sig_i_3_n_0 SLICE_X110Y33 LUT5 (Prop_lut5_I3_O) 0.327 2.527 r Hsync_sig_i_1/O net (fo=1, routed) 0.534 3.061 Hsync_sig_i_1_n_0 SLICE_X110Y33 FDRE r Hsync_sig_reg/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.692 38.619 clk_25MHz SLICE_X110Y33 FDRE r Hsync_sig_reg/C clock pessimism 0.619 39.237 clock uncertainty -0.098 39.140 SLICE_X110Y33 FDRE (Setup_fdre_C_R) -0.429 38.711 Hsync_sig_reg ------------------------------------------------------------------- required time 38.711 arrival time -3.061 ------------------------------------------------------------------- slack 35.650 Slack (MET) : 35.875ns (required time - arrival time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.921ns (logic 0.940ns (23.972%) route 2.981ns (76.028%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.063ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.381ns = ( 38.619 - 40.000 ) Source Clock Delay (SCD): -0.742ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.870 -0.742 clk_25MHz SLICE_X109Y33 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y33 FDRE (Prop_fdre_C_Q) 0.456 -0.286 f hor_cnt_reg[1]/Q net (fo=8, routed) 1.431 1.145 hor_cnt_reg_n_0_[1] SLICE_X109Y33 LUT5 (Prop_lut5_I1_O) 0.152 1.297 r hor_cnt[9]_i_2/O net (fo=4, routed) 0.758 2.055 hor_cnt[9]_i_2_n_0 SLICE_X111Y33 LUT4 (Prop_lut4_I2_O) 0.332 2.387 r hor_cnt[7]_i_1/O net (fo=1, routed) 0.792 3.180 hor_cnt[7] SLICE_X111Y33 FDRE r hor_cnt_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.692 38.619 clk_25MHz SLICE_X111Y33 FDRE r hor_cnt_reg[7]/C clock pessimism 0.577 39.195 clock uncertainty -0.098 39.098 SLICE_X111Y33 FDRE (Setup_fdre_C_D) -0.043 39.055 hor_cnt_reg[7] ------------------------------------------------------------------- required time 39.055 arrival time -3.180 ------------------------------------------------------------------- slack 35.875 Slack (MET) : 35.955ns (required time - arrival time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[6]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.656ns (logic 1.100ns (30.090%) route 2.556ns (69.910%)) Logic Levels: 2 (LUT3=1 LUT5=1) Clock Path Skew: -0.023ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.380ns = ( 38.620 - 40.000 ) Source Clock Delay (SCD): -0.741ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.871 -0.741 clk_25MHz SLICE_X113Y33 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y33 FDRE (Prop_fdre_C_Q) 0.419 -0.322 r ver_cnt_reg[1]/Q net (fo=17, routed) 1.133 0.811 ver_cnt_reg_n_0_[1] SLICE_X111Y34 LUT3 (Prop_lut3_I1_O) 0.327 1.138 r g0_b0__0/O net (fo=2, routed) 0.955 2.094 g0_b0__0_n_0 SLICE_X111Y33 LUT5 (Prop_lut5_I4_O) 0.354 2.448 r out_reg[6]_i_2/O net (fo=1, routed) 0.467 2.915 out_reg[6] SLICE_X113Y34 FDRE r out_reg_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.693 38.620 clk_25MHz SLICE_X113Y34 FDRE r out_reg_reg[6]/C clock pessimism 0.617 39.236 clock uncertainty -0.098 39.139 SLICE_X113Y34 FDRE (Setup_fdre_C_D) -0.269 38.870 out_reg_reg[6] ------------------------------------------------------------------- required time 38.870 arrival time -2.915 ------------------------------------------------------------------- slack 35.955 Slack (MET) : 36.079ns (required time - arrival time) Source: hor_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_10/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.330ns (logic 1.002ns (30.088%) route 2.328ns (69.912%)) Logic Levels: 2 (LUT3=1 LUT5=1) Clock Path Skew: -0.064ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.382ns = ( 38.618 - 40.000 ) Source Clock Delay (SCD): -0.742ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.870 -0.742 clk_25MHz SLICE_X108Y33 FDRE r hor_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y33 FDRE (Prop_fdre_C_Q) 0.518 -0.224 r hor_cnt_reg[8]/Q net (fo=9, routed) 0.838 0.614 current_digit[5] SLICE_X111Y33 LUT3 (Prop_lut3_I2_O) 0.152 0.766 f out_reg[6]_i_3/O net (fo=2, routed) 0.612 1.378 out_reg[6]_i_3_n_0 SLICE_X112Y33 LUT5 (Prop_lut5_I3_O) 0.332 1.710 r video_sig[11]_i_1/O net (fo=12, routed) 0.879 2.589 video_sig[11]_i_1_n_0 SLICE_X111Y32 FDRE r video_sig_reg[11]_lopt_replica_10/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.691 38.618 clk_25MHz SLICE_X111Y32 FDRE r video_sig_reg[11]_lopt_replica_10/C clock pessimism 0.577 39.194 clock uncertainty -0.098 39.097 SLICE_X111Y32 FDRE (Setup_fdre_C_R) -0.429 38.668 video_sig_reg[11]_lopt_replica_10 ------------------------------------------------------------------- required time 38.668 arrival time -2.589 ------------------------------------------------------------------- slack 36.079 Slack (MET) : 36.132ns (required time - arrival time) Source: hor_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.181ns (logic 1.002ns (31.504%) route 2.179ns (68.496%)) Logic Levels: 2 (LUT3=1 LUT5=1) Clock Path Skew: -0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.384ns = ( 38.616 - 40.000 ) Source Clock Delay (SCD): -0.742ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.870 -0.742 clk_25MHz SLICE_X108Y33 FDRE r hor_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y33 FDRE (Prop_fdre_C_Q) 0.518 -0.224 r hor_cnt_reg[8]/Q net (fo=9, routed) 0.838 0.614 current_digit[5] SLICE_X111Y33 LUT3 (Prop_lut3_I2_O) 0.152 0.766 f out_reg[6]_i_3/O net (fo=2, routed) 0.612 1.378 out_reg[6]_i_3_n_0 SLICE_X112Y33 LUT5 (Prop_lut5_I3_O) 0.332 1.710 r video_sig[11]_i_1/O net (fo=12, routed) 0.729 2.439 video_sig[11]_i_1_n_0 SLICE_X112Y31 FDRE r video_sig_reg[11]_lopt_replica/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.689 38.616 clk_25MHz SLICE_X112Y31 FDRE r video_sig_reg[11]_lopt_replica/C clock pessimism 0.577 39.192 clock uncertainty -0.098 39.095 SLICE_X112Y31 FDRE (Setup_fdre_C_R) -0.524 38.571 video_sig_reg[11]_lopt_replica ------------------------------------------------------------------- required time 38.571 arrival time -2.439 ------------------------------------------------------------------- slack 36.132 Slack (MET) : 36.132ns (required time - arrival time) Source: hor_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_4/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.181ns (logic 1.002ns (31.504%) route 2.179ns (68.496%)) Logic Levels: 2 (LUT3=1 LUT5=1) Clock Path Skew: -0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.384ns = ( 38.616 - 40.000 ) Source Clock Delay (SCD): -0.742ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.870 -0.742 clk_25MHz SLICE_X108Y33 FDRE r hor_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y33 FDRE (Prop_fdre_C_Q) 0.518 -0.224 r hor_cnt_reg[8]/Q net (fo=9, routed) 0.838 0.614 current_digit[5] SLICE_X111Y33 LUT3 (Prop_lut3_I2_O) 0.152 0.766 f out_reg[6]_i_3/O net (fo=2, routed) 0.612 1.378 out_reg[6]_i_3_n_0 SLICE_X112Y33 LUT5 (Prop_lut5_I3_O) 0.332 1.710 r video_sig[11]_i_1/O net (fo=12, routed) 0.729 2.439 video_sig[11]_i_1_n_0 SLICE_X112Y31 FDRE r video_sig_reg[11]_lopt_replica_4/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.689 38.616 clk_25MHz SLICE_X112Y31 FDRE r video_sig_reg[11]_lopt_replica_4/C clock pessimism 0.577 39.192 clock uncertainty -0.098 39.095 SLICE_X112Y31 FDRE (Setup_fdre_C_R) -0.524 38.571 video_sig_reg[11]_lopt_replica_4 ------------------------------------------------------------------- required time 38.571 arrival time -2.439 ------------------------------------------------------------------- slack 36.132 Slack (MET) : 36.132ns (required time - arrival time) Source: hor_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_5/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.181ns (logic 1.002ns (31.504%) route 2.179ns (68.496%)) Logic Levels: 2 (LUT3=1 LUT5=1) Clock Path Skew: -0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.384ns = ( 38.616 - 40.000 ) Source Clock Delay (SCD): -0.742ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.870 -0.742 clk_25MHz SLICE_X108Y33 FDRE r hor_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y33 FDRE (Prop_fdre_C_Q) 0.518 -0.224 r hor_cnt_reg[8]/Q net (fo=9, routed) 0.838 0.614 current_digit[5] SLICE_X111Y33 LUT3 (Prop_lut3_I2_O) 0.152 0.766 f out_reg[6]_i_3/O net (fo=2, routed) 0.612 1.378 out_reg[6]_i_3_n_0 SLICE_X112Y33 LUT5 (Prop_lut5_I3_O) 0.332 1.710 r video_sig[11]_i_1/O net (fo=12, routed) 0.729 2.439 video_sig[11]_i_1_n_0 SLICE_X112Y31 FDRE r video_sig_reg[11]_lopt_replica_5/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.689 38.616 clk_25MHz SLICE_X112Y31 FDRE r video_sig_reg[11]_lopt_replica_5/C clock pessimism 0.577 39.192 clock uncertainty -0.098 39.095 SLICE_X112Y31 FDRE (Setup_fdre_C_R) -0.524 38.571 video_sig_reg[11]_lopt_replica_5 ------------------------------------------------------------------- required time 38.571 arrival time -2.439 ------------------------------------------------------------------- slack 36.132 Slack (MET) : 36.132ns (required time - arrival time) Source: hor_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_6/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.181ns (logic 1.002ns (31.504%) route 2.179ns (68.496%)) Logic Levels: 2 (LUT3=1 LUT5=1) Clock Path Skew: -0.066ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.384ns = ( 38.616 - 40.000 ) Source Clock Delay (SCD): -0.742ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.870 -0.742 clk_25MHz SLICE_X108Y33 FDRE r hor_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y33 FDRE (Prop_fdre_C_Q) 0.518 -0.224 r hor_cnt_reg[8]/Q net (fo=9, routed) 0.838 0.614 current_digit[5] SLICE_X111Y33 LUT3 (Prop_lut3_I2_O) 0.152 0.766 f out_reg[6]_i_3/O net (fo=2, routed) 0.612 1.378 out_reg[6]_i_3_n_0 SLICE_X112Y33 LUT5 (Prop_lut5_I3_O) 0.332 1.710 r video_sig[11]_i_1/O net (fo=12, routed) 0.729 2.439 video_sig[11]_i_1_n_0 SLICE_X112Y31 FDRE r video_sig_reg[11]_lopt_replica_6/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.689 38.616 clk_25MHz SLICE_X112Y31 FDRE r video_sig_reg[11]_lopt_replica_6/C clock pessimism 0.577 39.192 clock uncertainty -0.098 39.095 SLICE_X112Y31 FDRE (Setup_fdre_C_R) -0.524 38.571 video_sig_reg[11]_lopt_replica_6 ------------------------------------------------------------------- required time 38.571 arrival time -2.439 ------------------------------------------------------------------- slack 36.132 Slack (MET) : 36.234ns (required time - arrival time) Source: hor_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.085ns (logic 1.002ns (32.481%) route 2.083ns (67.519%)) Logic Levels: 2 (LUT3=1 LUT5=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.378ns = ( 38.622 - 40.000 ) Source Clock Delay (SCD): -0.742ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.870 -0.742 clk_25MHz SLICE_X108Y33 FDRE r hor_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y33 FDRE (Prop_fdre_C_Q) 0.518 -0.224 r hor_cnt_reg[8]/Q net (fo=9, routed) 0.838 0.614 current_digit[5] SLICE_X111Y33 LUT3 (Prop_lut3_I2_O) 0.152 0.766 f out_reg[6]_i_3/O net (fo=2, routed) 0.612 1.378 out_reg[6]_i_3_n_0 SLICE_X112Y33 LUT5 (Prop_lut5_I3_O) 0.332 1.710 r video_sig[11]_i_1/O net (fo=12, routed) 0.633 2.343 video_sig[11]_i_1_n_0 SLICE_X112Y37 FDRE r video_sig_reg[11]/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.695 38.622 clk_25MHz SLICE_X112Y37 FDRE r video_sig_reg[11]/C clock pessimism 0.577 39.198 clock uncertainty -0.098 39.101 SLICE_X112Y37 FDRE (Setup_fdre_C_R) -0.524 38.577 video_sig_reg[11] ------------------------------------------------------------------- required time 38.577 arrival time -2.343 ------------------------------------------------------------------- slack 36.234 Slack (MET) : 36.234ns (required time - arrival time) Source: hor_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_11/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.085ns (logic 1.002ns (32.481%) route 2.083ns (67.519%)) Logic Levels: 2 (LUT3=1 LUT5=1) Clock Path Skew: -0.060ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.378ns = ( 38.622 - 40.000 ) Source Clock Delay (SCD): -0.742ns Clock Pessimism Removal (CPR): 0.577ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.870 -0.742 clk_25MHz SLICE_X108Y33 FDRE r hor_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y33 FDRE (Prop_fdre_C_Q) 0.518 -0.224 r hor_cnt_reg[8]/Q net (fo=9, routed) 0.838 0.614 current_digit[5] SLICE_X111Y33 LUT3 (Prop_lut3_I2_O) 0.152 0.766 f out_reg[6]_i_3/O net (fo=2, routed) 0.612 1.378 out_reg[6]_i_3_n_0 SLICE_X112Y33 LUT5 (Prop_lut5_I3_O) 0.332 1.710 r video_sig[11]_i_1/O net (fo=12, routed) 0.633 2.343 video_sig[11]_i_1_n_0 SLICE_X112Y37 FDRE r video_sig_reg[11]_lopt_replica_11/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 1.695 38.622 clk_25MHz SLICE_X112Y37 FDRE r video_sig_reg[11]_lopt_replica_11/C clock pessimism 0.577 39.198 clock uncertainty -0.098 39.101 SLICE_X112Y37 FDRE (Setup_fdre_C_R) -0.524 38.577 video_sig_reg[11]_lopt_replica_11 ------------------------------------------------------------------- required time 38.577 arrival time -2.343 ------------------------------------------------------------------- slack 36.234 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.174ns (arrival time - required time) Source: out_reg_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[3]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.308ns (logic 0.186ns (60.369%) route 0.122ns (39.631%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.780ns Source Clock Delay (SCD): -0.543ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.636 -0.543 clk_25MHz SLICE_X113Y34 FDRE r out_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.402 r out_reg_reg[4]/Q net (fo=1, routed) 0.122 -0.280 data1[3] SLICE_X112Y34 LUT6 (Prop_lut6_I0_O) 0.045 -0.235 r out_reg[3]_i_1/O net (fo=1, routed) 0.000 -0.235 out_reg[3] SLICE_X112Y34 FDRE r out_reg_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.905 -0.780 clk_25MHz SLICE_X112Y34 FDRE r out_reg_reg[3]/C clock pessimism 0.250 -0.530 SLICE_X112Y34 FDRE (Hold_fdre_C_D) 0.121 -0.409 out_reg_reg[3] ------------------------------------------------------------------- required time 0.409 arrival time -0.235 ------------------------------------------------------------------- slack 0.174 Slack (MET) : 0.198ns (arrival time - required time) Source: out_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_7/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.272ns (logic 0.141ns (51.913%) route 0.131ns (48.087%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.779ns Source Clock Delay (SCD): -0.543ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.636 -0.543 clk_25MHz SLICE_X111Y34 FDRE r out_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.402 r out_reg_reg[0]/Q net (fo=12, routed) 0.131 -0.271 out_reg_reg_n_0_[0] SLICE_X112Y35 FDRE r video_sig_reg[11]_lopt_replica_7/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.906 -0.779 clk_25MHz SLICE_X112Y35 FDRE r video_sig_reg[11]_lopt_replica_7/C clock pessimism 0.251 -0.528 SLICE_X112Y35 FDRE (Hold_fdre_C_D) 0.059 -0.469 video_sig_reg[11]_lopt_replica_7 ------------------------------------------------------------------- required time 0.469 arrival time -0.271 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.198ns (arrival time - required time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.332ns (logic 0.186ns (55.943%) route 0.146ns (44.057%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.634 -0.545 clk_25MHz SLICE_X113Y32 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.404 r ver_cnt_reg[0]/Q net (fo=17, routed) 0.146 -0.257 ver_cnt_reg_n_0_[0] SLICE_X112Y32 LUT6 (Prop_lut6_I4_O) 0.045 -0.212 r ver_cnt[9]_i_2/O net (fo=1, routed) 0.000 -0.212 ver_cnt[9]_i_2_n_0 SLICE_X112Y32 FDRE r ver_cnt_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.903 -0.782 clk_25MHz SLICE_X112Y32 FDRE r ver_cnt_reg[9]/C clock pessimism 0.250 -0.532 SLICE_X112Y32 FDRE (Hold_fdre_C_D) 0.121 -0.411 ver_cnt_reg[9] ------------------------------------------------------------------- required time 0.411 arrival time -0.212 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.202ns (arrival time - required time) Source: ver_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.306ns (logic 0.209ns (68.401%) route 0.097ns (31.599%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.634 -0.545 clk_25MHz SLICE_X112Y32 FDRE r ver_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.381 f ver_cnt_reg[9]/Q net (fo=7, routed) 0.097 -0.284 ver_cnt_reg_n_0_[9] SLICE_X113Y32 LUT6 (Prop_lut6_I2_O) 0.045 -0.239 r ver_cnt[2]_i_1/O net (fo=1, routed) 0.000 -0.239 ver_cnt[2]_i_1_n_0 SLICE_X113Y32 FDRE r ver_cnt_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.903 -0.782 clk_25MHz SLICE_X113Y32 FDRE r ver_cnt_reg[2]/C clock pessimism 0.250 -0.532 SLICE_X113Y32 FDRE (Hold_fdre_C_D) 0.091 -0.441 ver_cnt_reg[2] ------------------------------------------------------------------- required time 0.441 arrival time -0.239 ------------------------------------------------------------------- slack 0.202 Slack (MET) : 0.204ns (arrival time - required time) Source: hor_cnt_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.359ns (logic 0.186ns (51.808%) route 0.173ns (48.192%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.635 -0.544 clk_25MHz SLICE_X111Y33 FDRE r hor_cnt_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y33 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r hor_cnt_reg[6]/Q net (fo=11, routed) 0.173 -0.230 current_digit[3] SLICE_X108Y33 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r hor_cnt[8]_i_1/O net (fo=1, routed) 0.000 -0.185 hor_cnt[8] SLICE_X108Y33 FDRE r hor_cnt_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.903 -0.782 clk_25MHz SLICE_X108Y33 FDRE r hor_cnt_reg[8]/C clock pessimism 0.273 -0.509 SLICE_X108Y33 FDRE (Hold_fdre_C_D) 0.120 -0.389 hor_cnt_reg[8] ------------------------------------------------------------------- required time 0.389 arrival time -0.185 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.205ns (arrival time - required time) Source: out_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_8/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.272ns (logic 0.141ns (51.913%) route 0.131ns (48.087%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.779ns Source Clock Delay (SCD): -0.543ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.636 -0.543 clk_25MHz SLICE_X111Y34 FDRE r out_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.402 r out_reg_reg[0]/Q net (fo=12, routed) 0.131 -0.271 out_reg_reg_n_0_[0] SLICE_X112Y35 FDRE r video_sig_reg[11]_lopt_replica_8/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.906 -0.779 clk_25MHz SLICE_X112Y35 FDRE r video_sig_reg[11]_lopt_replica_8/C clock pessimism 0.251 -0.528 SLICE_X112Y35 FDRE (Hold_fdre_C_D) 0.052 -0.476 video_sig_reg[11]_lopt_replica_8 ------------------------------------------------------------------- required time 0.476 arrival time -0.271 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.219ns (arrival time - required time) Source: ver_cnt_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.311ns (logic 0.227ns (73.093%) route 0.084ns (26.907%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.237ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.634 -0.545 clk_25MHz SLICE_X113Y32 FDRE r ver_cnt_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y32 FDRE (Prop_fdre_C_Q) 0.128 -0.417 r ver_cnt_reg[4]/Q net (fo=8, routed) 0.084 -0.333 ver_cnt_reg_n_0_[4] SLICE_X113Y32 LUT6 (Prop_lut6_I0_O) 0.099 -0.234 r ver_cnt[5]_i_1/O net (fo=1, routed) 0.000 -0.234 ver_cnt[5]_i_1_n_0 SLICE_X113Y32 FDRE r ver_cnt_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.903 -0.782 clk_25MHz SLICE_X113Y32 FDRE r ver_cnt_reg[5]/C clock pessimism 0.237 -0.545 SLICE_X113Y32 FDRE (Hold_fdre_C_D) 0.092 -0.453 ver_cnt_reg[5] ------------------------------------------------------------------- required time 0.453 arrival time -0.234 ------------------------------------------------------------------- slack 0.219 Slack (MET) : 0.228ns (arrival time - required time) Source: ver_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.349ns (logic 0.246ns (70.553%) route 0.103ns (29.447%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.237ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.634 -0.545 clk_25MHz SLICE_X112Y32 FDRE r ver_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y32 FDRE (Prop_fdre_C_Q) 0.148 -0.397 r ver_cnt_reg[7]/Q net (fo=5, routed) 0.103 -0.294 ver_cnt_reg_n_0_[7] SLICE_X112Y32 LUT6 (Prop_lut6_I4_O) 0.098 -0.196 r ver_cnt[8]_i_1/O net (fo=1, routed) 0.000 -0.196 ver_cnt[8]_i_1_n_0 SLICE_X112Y32 FDRE r ver_cnt_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.903 -0.782 clk_25MHz SLICE_X112Y32 FDRE r ver_cnt_reg[8]/C clock pessimism 0.237 -0.545 SLICE_X112Y32 FDRE (Hold_fdre_C_D) 0.121 -0.424 ver_cnt_reg[8] ------------------------------------------------------------------- required time 0.424 arrival time -0.196 ------------------------------------------------------------------- slack 0.228 Slack (MET) : 0.229ns (arrival time - required time) Source: ver_cnt_reg[5]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.373ns (logic 0.187ns (50.195%) route 0.186ns (49.805%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.782ns Source Clock Delay (SCD): -0.545ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.634 -0.545 clk_25MHz SLICE_X113Y32 FDRE r ver_cnt_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.404 r ver_cnt_reg[5]/Q net (fo=7, routed) 0.186 -0.218 ver_cnt_reg_n_0_[5] SLICE_X112Y32 LUT5 (Prop_lut5_I1_O) 0.046 -0.172 r ver_cnt[7]_i_1/O net (fo=1, routed) 0.000 -0.172 ver_cnt[7]_i_1_n_0 SLICE_X112Y32 FDRE r ver_cnt_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.903 -0.782 clk_25MHz SLICE_X112Y32 FDRE r ver_cnt_reg[7]/C clock pessimism 0.250 -0.532 SLICE_X112Y32 FDRE (Hold_fdre_C_D) 0.131 -0.401 ver_cnt_reg[7] ------------------------------------------------------------------- required time 0.401 arrival time -0.172 ------------------------------------------------------------------- slack 0.229 Slack (MET) : 0.230ns (arrival time - required time) Source: out_reg_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.322ns (logic 0.186ns (57.733%) route 0.136ns (42.267%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.780ns Source Clock Delay (SCD): -0.543ns Clock Pessimism Removal (CPR): -0.237ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.636 -0.543 clk_25MHz SLICE_X113Y34 FDRE r out_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X113Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.402 r out_reg_reg[6]/Q net (fo=1, routed) 0.136 -0.265 data1[5] SLICE_X113Y34 LUT6 (Prop_lut6_I2_O) 0.045 -0.220 r out_reg[5]_i_1/O net (fo=1, routed) 0.000 -0.220 out_reg[5] SLICE_X113Y34 FDRE r out_reg_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=41, routed) 0.905 -0.780 clk_25MHz SLICE_X113Y34 FDRE r out_reg_reg[5]/C clock pessimism 0.237 -0.543 SLICE_X113Y34 FDRE (Hold_fdre_C_D) 0.092 -0.451 out_reg_reg[5] ------------------------------------------------------------------- required time 0.451 arrival time -0.220 ------------------------------------------------------------------- slack 0.230 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out_clk_100MHz_to_25MHz Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y0 clk_converter/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X110Y33 Hsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X112Y33 Vsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y33 hor_cnt_reg[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X109Y33 hor_cnt_reg[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X109Y33 hor_cnt_reg[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y33 hor_cnt_reg[3]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X109Y33 hor_cnt_reg[4]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X108Y33 hor_cnt_reg[5]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X110Y33 Hsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y33 Vsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y33 hor_cnt_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y33 hor_cnt_reg[3]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y33 hor_cnt_reg[6]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y33 hor_cnt_reg[7]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y33 ver_cnt_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y33 ver_cnt_reg[3]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y37 video_sig_reg[11]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y31 video_sig_reg[11]_lopt_replica/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X110Y33 Hsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y33 Vsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y33 hor_cnt_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y33 hor_cnt_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y33 hor_cnt_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y33 hor_cnt_reg[3]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y33 hor_cnt_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X108Y33 hor_cnt_reg[5]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y33 hor_cnt_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y33 hor_cnt_reg[7]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_100MHz_to_25MHz To Clock: clkfbout_clk_100MHz_to_25MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_100MHz_to_25MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 clk_converter/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT