Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Fri Oct 13 09:21:39 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_power -file clock_counter_power_routed.rpt -pb clock_counter_power_summary_routed.pb -rpx clock_counter_power_routed.rpx | Design : clock_counter | Device : xc7z020clg484-1 | Design State : routed | Grade : commercial | Process : typical | Characterization : Production ------------------------------------------------------------------------------------------------------------------------------------------------------------- Power Report Table of Contents ----------------- 1. Summary 1.1 On-Chip Components 1.2 Power Supply Summary 1.3 Confidence Level 2. Settings 2.1 Environment 2.2 Clock Constraints 3. Detailed Reports 3.1 By Hierarchy 1. Summary ---------- +--------------------------+---------------------------------+ | Total On-Chip Power (W) | 6.429 (Junction temp exceeded!) | | Dynamic (W) | 5.944 | | Device Static (W) | 0.485 | | Effective TJA (C/W) | 11.5 | | Max Ambient (C) | 10.9 | | Junction Temperature (C) | 99.1 | | Confidence Level | Low | | Setting File | --- | | Simulation Activity File | --- | | Design Nets Matched | NA | +--------------------------+---------------------------------+ 1.1 On-Chip Components ---------------------- +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ | Slice Logic | 0.034 | 39 | --- | --- | | CARRY4 | 0.016 | 7 | 13300 | 0.05 | | Register | 0.012 | 28 | 106400 | 0.03 | | BUFG | 0.006 | 1 | 32 | 3.13 | | LUT as Logic | 0.001 | 1 | 53200 | <0.01 | | Others | 0.000 | 2 | --- | --- | | Signals | 0.076 | 36 | --- | --- | | I/O | 5.834 | 9 | 200 | 4.50 | | Static Power | 0.485 | | | | | Total | 6.429 | | | | +----------------+-----------+----------+-----------+-----------------+ 1.2 Power Supply Summary ------------------------ +-----------+-------------+-----------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | +-----------+-------------+-----------+-------------+------------+ | Vccint | 1.000 | 0.241 | 0.114 | 0.127 | | Vccaux | 1.800 | 0.266 | 0.214 | 0.052 | | Vcco33 | 3.300 | 1.651 | 1.650 | 0.001 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | | Vccbram | 1.000 | 0.009 | 0.000 | 0.009 | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | | MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | | Vccpint | 1.000 | 0.192 | 0.000 | 0.192 | | Vccpaux | 1.800 | 0.010 | 0.000 | 0.010 | | Vccpll | 1.800 | 0.003 | 0.000 | 0.003 | | Vcco_ddr | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco_mio0 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco_mio1 | 1.800 | 0.000 | 0.000 | 0.000 | | Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | +-----------+-------------+-----------+-------------+------------+ 1.3 Confidence Level -------------------- +-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ | User Input Data | Confidence | Details | Action | +-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ | Design implementation state | High | Design is routed | | | Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | | I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | | Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | | Device models | High | Device models are Production | | | | | | | | Overall confidence level | Low | | | +-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ 2. Settings ----------- 2.1 Environment --------------- +-----------------------+------------------------+ | Ambient Temp (C) | 25.0 | | ThetaJA (C/W) | 11.5 | | Airflow (LFM) | 250 | | Heat Sink | none | | ThetaSA (C/W) | 0.0 | | Board Selection | medium (10"x10") | | # of Board Layers | 8to11 (8 to 11 Layers) | | Board Temperature (C) | 25.0 | +-----------------------+------------------------+ 2.2 Clock Constraints --------------------- +-------+--------+-----------------+ | Clock | Domain | Constraint (ns) | +-------+--------+-----------------+ 3. Detailed Reports ------------------- 3.1 By Hierarchy ---------------- +---------------+-----------+ | Name | Power (W) | +---------------+-----------+ | clock_counter | 5.944 | +---------------+-----------+