Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Fri Oct 27 11:18:44 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_timing_summary -warn_on_violation -max_paths 10 -file chars_timing_summary_routed.rpt -rpx chars_timing_summary_routed.rpx | Design : chars | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 --------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 0 input ports with no input delay specified. There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 14 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 35.435 0.000 0 99 0.140 0.000 0 99 3.000 0.000 0 51 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk_100MHz {0.000 5.000} 10.000 100.000 clk_out_clk_100MHz_to_25MHz {0.000 20.000} 40.000 25.000 clkfbout_clk_100MHz_to_25MHz {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk_100MHz 3.000 0.000 0 1 clk_out_clk_100MHz_to_25MHz 35.435 0.000 0 99 0.140 0.000 0 99 19.500 0.000 0 47 clkfbout_clk_100MHz_to_25MHz 7.845 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk_100MHz To Clock: clk_100MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100MHz } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out_clk_100MHz_to_25MHz To Clock: clk_out_clk_100MHz_to_25MHz Setup : 0 Failing Endpoints, Worst Slack 35.435ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.140ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 35.435ns (required time - arrival time) Source: ver_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 4.024ns (logic 1.125ns (27.959%) route 2.899ns (72.041%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.377ns = ( 38.623 - 40.000 ) Source Clock Delay (SCD): -0.746ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.866 -0.746 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y29 FDRE (Prop_fdre_C_Q) 0.478 -0.268 r ver_cnt_reg[8]/Q net (fo=5, routed) 0.901 0.634 ver_cnt_reg_n_0_[8] SLICE_X112Y28 LUT4 (Prop_lut4_I3_O) 0.319 0.953 f Vsync_sig_i_5/O net (fo=3, routed) 0.499 1.452 Vsync_sig_i_5_n_0 SLICE_X112Y28 LUT5 (Prop_lut5_I0_O) 0.328 1.780 r video_sig[11]_i_1/O net (fo=12, routed) 1.498 3.278 p_0_in SLICE_X113Y38 FDRE r video_sig_reg[11]/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.696 38.623 clk_25MHz SLICE_X113Y38 FDRE r video_sig_reg[11]/C clock pessimism 0.617 39.239 clock uncertainty -0.098 39.142 SLICE_X113Y38 FDRE (Setup_fdre_C_R) -0.429 38.713 video_sig_reg[11] ------------------------------------------------------------------- required time 38.713 arrival time -3.278 ------------------------------------------------------------------- slack 35.435 Slack (MET) : 35.435ns (required time - arrival time) Source: ver_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_11/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 4.024ns (logic 1.125ns (27.959%) route 2.899ns (72.041%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.015ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.377ns = ( 38.623 - 40.000 ) Source Clock Delay (SCD): -0.746ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.866 -0.746 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y29 FDRE (Prop_fdre_C_Q) 0.478 -0.268 r ver_cnt_reg[8]/Q net (fo=5, routed) 0.901 0.634 ver_cnt_reg_n_0_[8] SLICE_X112Y28 LUT4 (Prop_lut4_I3_O) 0.319 0.953 f Vsync_sig_i_5/O net (fo=3, routed) 0.499 1.452 Vsync_sig_i_5_n_0 SLICE_X112Y28 LUT5 (Prop_lut5_I0_O) 0.328 1.780 r video_sig[11]_i_1/O net (fo=12, routed) 1.498 3.278 p_0_in SLICE_X113Y38 FDRE r video_sig_reg[11]_lopt_replica_11/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.696 38.623 clk_25MHz SLICE_X113Y38 FDRE r video_sig_reg[11]_lopt_replica_11/C clock pessimism 0.617 39.239 clock uncertainty -0.098 39.142 SLICE_X113Y38 FDRE (Setup_fdre_C_R) -0.429 38.713 video_sig_reg[11]_lopt_replica_11 ------------------------------------------------------------------- required time 38.713 arrival time -3.278 ------------------------------------------------------------------- slack 35.435 Slack (MET) : 35.572ns (required time - arrival time) Source: ver_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_2/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.885ns (logic 1.125ns (28.955%) route 2.760ns (71.045%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.378ns = ( 38.622 - 40.000 ) Source Clock Delay (SCD): -0.746ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.866 -0.746 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y29 FDRE (Prop_fdre_C_Q) 0.478 -0.268 r ver_cnt_reg[8]/Q net (fo=5, routed) 0.901 0.634 ver_cnt_reg_n_0_[8] SLICE_X112Y28 LUT4 (Prop_lut4_I3_O) 0.319 0.953 f Vsync_sig_i_5/O net (fo=3, routed) 0.499 1.452 Vsync_sig_i_5_n_0 SLICE_X112Y28 LUT5 (Prop_lut5_I0_O) 0.328 1.780 r video_sig[11]_i_1/O net (fo=12, routed) 1.360 3.140 p_0_in SLICE_X113Y37 FDRE r video_sig_reg[11]_lopt_replica_2/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.695 38.622 clk_25MHz SLICE_X113Y37 FDRE r video_sig_reg[11]_lopt_replica_2/C clock pessimism 0.617 39.238 clock uncertainty -0.098 39.141 SLICE_X113Y37 FDRE (Setup_fdre_C_R) -0.429 38.712 video_sig_reg[11]_lopt_replica_2 ------------------------------------------------------------------- required time 38.712 arrival time -3.140 ------------------------------------------------------------------- slack 35.572 Slack (MET) : 35.572ns (required time - arrival time) Source: ver_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_3/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.885ns (logic 1.125ns (28.955%) route 2.760ns (71.045%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.378ns = ( 38.622 - 40.000 ) Source Clock Delay (SCD): -0.746ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.866 -0.746 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y29 FDRE (Prop_fdre_C_Q) 0.478 -0.268 r ver_cnt_reg[8]/Q net (fo=5, routed) 0.901 0.634 ver_cnt_reg_n_0_[8] SLICE_X112Y28 LUT4 (Prop_lut4_I3_O) 0.319 0.953 f Vsync_sig_i_5/O net (fo=3, routed) 0.499 1.452 Vsync_sig_i_5_n_0 SLICE_X112Y28 LUT5 (Prop_lut5_I0_O) 0.328 1.780 r video_sig[11]_i_1/O net (fo=12, routed) 1.360 3.140 p_0_in SLICE_X113Y37 FDRE r video_sig_reg[11]_lopt_replica_3/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.695 38.622 clk_25MHz SLICE_X113Y37 FDRE r video_sig_reg[11]_lopt_replica_3/C clock pessimism 0.617 39.238 clock uncertainty -0.098 39.141 SLICE_X113Y37 FDRE (Setup_fdre_C_R) -0.429 38.712 video_sig_reg[11]_lopt_replica_3 ------------------------------------------------------------------- required time 38.712 arrival time -3.140 ------------------------------------------------------------------- slack 35.572 Slack (MET) : 35.860ns (required time - arrival time) Source: ver_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_7/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.596ns (logic 1.125ns (31.283%) route 2.471ns (68.717%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.379ns = ( 38.621 - 40.000 ) Source Clock Delay (SCD): -0.746ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.866 -0.746 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y29 FDRE (Prop_fdre_C_Q) 0.478 -0.268 r ver_cnt_reg[8]/Q net (fo=5, routed) 0.901 0.634 ver_cnt_reg_n_0_[8] SLICE_X112Y28 LUT4 (Prop_lut4_I3_O) 0.319 0.953 f Vsync_sig_i_5/O net (fo=3, routed) 0.499 1.452 Vsync_sig_i_5_n_0 SLICE_X112Y28 LUT5 (Prop_lut5_I0_O) 0.328 1.780 r video_sig[11]_i_1/O net (fo=12, routed) 1.071 2.851 p_0_in SLICE_X113Y35 FDRE r video_sig_reg[11]_lopt_replica_7/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.694 38.621 clk_25MHz SLICE_X113Y35 FDRE r video_sig_reg[11]_lopt_replica_7/C clock pessimism 0.617 39.237 clock uncertainty -0.098 39.140 SLICE_X113Y35 FDRE (Setup_fdre_C_R) -0.429 38.711 video_sig_reg[11]_lopt_replica_7 ------------------------------------------------------------------- required time 38.711 arrival time -2.851 ------------------------------------------------------------------- slack 35.860 Slack (MET) : 35.860ns (required time - arrival time) Source: ver_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_8/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.596ns (logic 1.125ns (31.283%) route 2.471ns (68.717%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.017ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.379ns = ( 38.621 - 40.000 ) Source Clock Delay (SCD): -0.746ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.866 -0.746 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y29 FDRE (Prop_fdre_C_Q) 0.478 -0.268 r ver_cnt_reg[8]/Q net (fo=5, routed) 0.901 0.634 ver_cnt_reg_n_0_[8] SLICE_X112Y28 LUT4 (Prop_lut4_I3_O) 0.319 0.953 f Vsync_sig_i_5/O net (fo=3, routed) 0.499 1.452 Vsync_sig_i_5_n_0 SLICE_X112Y28 LUT5 (Prop_lut5_I0_O) 0.328 1.780 r video_sig[11]_i_1/O net (fo=12, routed) 1.071 2.851 p_0_in SLICE_X113Y35 FDRE r video_sig_reg[11]_lopt_replica_8/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.694 38.621 clk_25MHz SLICE_X113Y35 FDRE r video_sig_reg[11]_lopt_replica_8/C clock pessimism 0.617 39.237 clock uncertainty -0.098 39.140 SLICE_X113Y35 FDRE (Setup_fdre_C_R) -0.429 38.711 video_sig_reg[11]_lopt_replica_8 ------------------------------------------------------------------- required time 38.711 arrival time -2.851 ------------------------------------------------------------------- slack 35.860 Slack (MET) : 36.112ns (required time - arrival time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[6]/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.242ns (logic 0.932ns (28.744%) route 2.310ns (71.256%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.385ns = ( 38.615 - 40.000 ) Source Clock Delay (SCD): -0.745ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.867 -0.745 clk_25MHz SLICE_X111Y30 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y30 FDRE (Prop_fdre_C_Q) 0.456 -0.289 r hor_cnt_reg[1]/Q net (fo=15, routed) 1.114 0.826 hor_cnt_reg_n_0_[1] SLICE_X111Y31 LUT5 (Prop_lut5_I1_O) 0.150 0.976 f hor_cnt[9]_i_3/O net (fo=7, routed) 0.608 1.583 hor_cnt[9]_i_3_n_0 SLICE_X112Y29 LUT5 (Prop_lut5_I3_O) 0.326 1.909 r ver_cnt[9]_i_1/O net (fo=9, routed) 0.588 2.498 ver_cnt[9]_i_1_n_0 SLICE_X112Y29 FDRE r ver_cnt_reg[6]/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.688 38.615 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[6]/C clock pessimism 0.617 39.231 clock uncertainty -0.098 39.134 SLICE_X112Y29 FDRE (Setup_fdre_C_R) -0.524 38.610 ver_cnt_reg[6] ------------------------------------------------------------------- required time 38.610 arrival time -2.498 ------------------------------------------------------------------- slack 36.112 Slack (MET) : 36.112ns (required time - arrival time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[7]/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.242ns (logic 0.932ns (28.744%) route 2.310ns (71.256%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.385ns = ( 38.615 - 40.000 ) Source Clock Delay (SCD): -0.745ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.867 -0.745 clk_25MHz SLICE_X111Y30 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y30 FDRE (Prop_fdre_C_Q) 0.456 -0.289 r hor_cnt_reg[1]/Q net (fo=15, routed) 1.114 0.826 hor_cnt_reg_n_0_[1] SLICE_X111Y31 LUT5 (Prop_lut5_I1_O) 0.150 0.976 f hor_cnt[9]_i_3/O net (fo=7, routed) 0.608 1.583 hor_cnt[9]_i_3_n_0 SLICE_X112Y29 LUT5 (Prop_lut5_I3_O) 0.326 1.909 r ver_cnt[9]_i_1/O net (fo=9, routed) 0.588 2.498 ver_cnt[9]_i_1_n_0 SLICE_X112Y29 FDRE r ver_cnt_reg[7]/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.688 38.615 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[7]/C clock pessimism 0.617 39.231 clock uncertainty -0.098 39.134 SLICE_X112Y29 FDRE (Setup_fdre_C_R) -0.524 38.610 ver_cnt_reg[7] ------------------------------------------------------------------- required time 38.610 arrival time -2.498 ------------------------------------------------------------------- slack 36.112 Slack (MET) : 36.112ns (required time - arrival time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[8]/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.242ns (logic 0.932ns (28.744%) route 2.310ns (71.256%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.385ns = ( 38.615 - 40.000 ) Source Clock Delay (SCD): -0.745ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.867 -0.745 clk_25MHz SLICE_X111Y30 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y30 FDRE (Prop_fdre_C_Q) 0.456 -0.289 r hor_cnt_reg[1]/Q net (fo=15, routed) 1.114 0.826 hor_cnt_reg_n_0_[1] SLICE_X111Y31 LUT5 (Prop_lut5_I1_O) 0.150 0.976 f hor_cnt[9]_i_3/O net (fo=7, routed) 0.608 1.583 hor_cnt[9]_i_3_n_0 SLICE_X112Y29 LUT5 (Prop_lut5_I3_O) 0.326 1.909 r ver_cnt[9]_i_1/O net (fo=9, routed) 0.588 2.498 ver_cnt[9]_i_1_n_0 SLICE_X112Y29 FDRE r ver_cnt_reg[8]/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.688 38.615 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[8]/C clock pessimism 0.617 39.231 clock uncertainty -0.098 39.134 SLICE_X112Y29 FDRE (Setup_fdre_C_R) -0.524 38.610 ver_cnt_reg[8] ------------------------------------------------------------------- required time 38.610 arrival time -2.498 ------------------------------------------------------------------- slack 36.112 Slack (MET) : 36.112ns (required time - arrival time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[9]/R (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100MHz_to_25MHz rise@40.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 3.242ns (logic 0.932ns (28.744%) route 2.310ns (71.256%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.385ns = ( 38.615 - 40.000 ) Source Clock Delay (SCD): -0.745ns Clock Pessimism Removal (CPR): 0.617ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.867 -0.745 clk_25MHz SLICE_X111Y30 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y30 FDRE (Prop_fdre_C_Q) 0.456 -0.289 r hor_cnt_reg[1]/Q net (fo=15, routed) 1.114 0.826 hor_cnt_reg_n_0_[1] SLICE_X111Y31 LUT5 (Prop_lut5_I1_O) 0.150 0.976 f hor_cnt[9]_i_3/O net (fo=7, routed) 0.608 1.583 hor_cnt[9]_i_3_n_0 SLICE_X112Y29 LUT5 (Prop_lut5_I3_O) 0.326 1.909 r ver_cnt[9]_i_1/O net (fo=9, routed) 0.588 2.498 ver_cnt[9]_i_1_n_0 SLICE_X112Y29 FDRE r ver_cnt_reg[9]/R ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 1.688 38.615 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[9]/C clock pessimism 0.617 39.231 clock uncertainty -0.098 39.134 SLICE_X112Y29 FDRE (Setup_fdre_C_R) -0.524 38.610 ver_cnt_reg[9] ------------------------------------------------------------------- required time 38.610 arrival time -2.498 ------------------------------------------------------------------- slack 36.112 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.140ns (arrival time - required time) Source: out_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.273ns (logic 0.186ns (68.106%) route 0.087ns (31.894%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.784ns Source Clock Delay (SCD): -0.547ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.632 -0.547 clk_25MHz SLICE_X109Y31 FDRE r out_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X109Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r out_reg_reg[2]/Q net (fo=1, routed) 0.087 -0.319 data1[1] SLICE_X108Y31 LUT5 (Prop_lut5_I0_O) 0.045 -0.274 r out_reg[1]_i_1/O net (fo=1, routed) 0.000 -0.274 out_reg[1] SLICE_X108Y31 FDRE r out_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.901 -0.784 clk_25MHz SLICE_X108Y31 FDRE r out_reg_reg[1]/C clock pessimism 0.250 -0.534 SLICE_X108Y31 FDRE (Hold_fdre_C_D) 0.120 -0.414 out_reg_reg[1] ------------------------------------------------------------------- required time 0.414 arrival time -0.274 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.180ns (arrival time - required time) Source: out_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_6/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.265ns (logic 0.141ns (53.157%) route 0.124ns (46.843%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.784ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.633 -0.546 clk_25MHz SLICE_X110Y31 FDRE r out_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.405 r out_reg_reg[0]/Q net (fo=12, routed) 0.124 -0.280 out_reg_reg_n_0_[0] SLICE_X113Y30 FDRE r video_sig_reg[11]_lopt_replica_6/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.901 -0.784 clk_25MHz SLICE_X113Y30 FDRE r video_sig_reg[11]_lopt_replica_6/C clock pessimism 0.251 -0.533 SLICE_X113Y30 FDRE (Hold_fdre_C_D) 0.072 -0.461 video_sig_reg[11]_lopt_replica_6 ------------------------------------------------------------------- required time 0.461 arrival time -0.280 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.188ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.292ns (logic 0.186ns (63.700%) route 0.106ns (36.300%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.784ns Source Clock Delay (SCD): -0.547ns Clock Pessimism Removal (CPR): -0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.632 -0.547 clk_25MHz SLICE_X111Y30 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r hor_cnt_reg[1]/Q net (fo=15, routed) 0.106 -0.300 hor_cnt_reg_n_0_[1] SLICE_X110Y30 LUT5 (Prop_lut5_I2_O) 0.045 -0.255 r out_reg[5]_i_1/O net (fo=1, routed) 0.000 -0.255 out_reg[5] SLICE_X110Y30 FDRE r out_reg_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.901 -0.784 clk_25MHz SLICE_X110Y30 FDRE r out_reg_reg[5]/C clock pessimism 0.250 -0.534 SLICE_X110Y30 FDRE (Hold_fdre_C_D) 0.091 -0.443 out_reg_reg[5] ------------------------------------------------------------------- required time 0.443 arrival time -0.255 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.200ns (arrival time - required time) Source: out_reg_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.329ns (logic 0.209ns (63.467%) route 0.120ns (36.533%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.783ns Source Clock Delay (SCD): -0.547ns Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.632 -0.547 clk_25MHz SLICE_X108Y31 FDRE r out_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X108Y31 FDRE (Prop_fdre_C_Q) 0.164 -0.383 r out_reg_reg[1]/Q net (fo=1, routed) 0.120 -0.262 data1[0] SLICE_X110Y31 LUT5 (Prop_lut5_I0_O) 0.045 -0.217 r out_reg[0]_i_1/O net (fo=1, routed) 0.000 -0.217 out_reg[0] SLICE_X110Y31 FDRE r out_reg_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.902 -0.783 clk_25MHz SLICE_X110Y31 FDRE r out_reg_reg[0]/C clock pessimism 0.273 -0.510 SLICE_X110Y31 FDRE (Hold_fdre_C_D) 0.092 -0.418 out_reg_reg[0] ------------------------------------------------------------------- required time 0.418 arrival time -0.217 ------------------------------------------------------------------- slack 0.200 Slack (MET) : 0.212ns (arrival time - required time) Source: ver_cnt_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.333ns (logic 0.246ns (73.853%) route 0.087ns (26.147%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.785ns Source Clock Delay (SCD): -0.548ns Clock Pessimism Removal (CPR): -0.237ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.631 -0.548 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X112Y29 FDRE (Prop_fdre_C_Q) 0.148 -0.400 r ver_cnt_reg[8]/Q net (fo=5, routed) 0.087 -0.313 ver_cnt_reg_n_0_[8] SLICE_X112Y29 LUT6 (Prop_lut6_I3_O) 0.098 -0.215 r ver_cnt[9]_i_2/O net (fo=1, routed) 0.000 -0.215 ver_cnt[9]_i_2_n_0 SLICE_X112Y29 FDRE r ver_cnt_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.900 -0.785 clk_25MHz SLICE_X112Y29 FDRE r ver_cnt_reg[9]/C clock pessimism 0.237 -0.548 SLICE_X112Y29 FDRE (Hold_fdre_C_D) 0.121 -0.427 ver_cnt_reg[9] ------------------------------------------------------------------- required time 0.427 arrival time -0.215 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.235ns (arrival time - required time) Source: hor_cnt_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.361ns (logic 0.186ns (51.534%) route 0.175ns (48.466%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.784ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.633 -0.546 clk_25MHz SLICE_X111Y31 FDRE r hor_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.405 r hor_cnt_reg[2]/Q net (fo=14, routed) 0.175 -0.230 hor_cnt_reg_n_0_[2] SLICE_X109Y31 LUT5 (Prop_lut5_I1_O) 0.045 -0.185 r out_reg[2]_i_1/O net (fo=1, routed) 0.000 -0.185 out_reg[2] SLICE_X109Y31 FDRE r out_reg_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.901 -0.784 clk_25MHz SLICE_X109Y31 FDRE r out_reg_reg[2]/C clock pessimism 0.273 -0.511 SLICE_X109Y31 FDRE (Hold_fdre_C_D) 0.091 -0.420 out_reg_reg[2] ------------------------------------------------------------------- required time 0.420 arrival time -0.185 ------------------------------------------------------------------- slack 0.235 Slack (MET) : 0.238ns (arrival time - required time) Source: out_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_10/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.324ns (logic 0.141ns (43.541%) route 0.183ns (56.459%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.781ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.633 -0.546 clk_25MHz SLICE_X110Y31 FDRE r out_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.405 r out_reg_reg[0]/Q net (fo=12, routed) 0.183 -0.222 out_reg_reg_n_0_[0] SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_10/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.904 -0.781 clk_25MHz SLICE_X113Y33 FDRE r video_sig_reg[11]_lopt_replica_10/C clock pessimism 0.251 -0.530 SLICE_X113Y33 FDRE (Hold_fdre_C_D) 0.070 -0.460 video_sig_reg[11]_lopt_replica_10 ------------------------------------------------------------------- required time 0.460 arrival time -0.222 ------------------------------------------------------------------- slack 0.238 Slack (MET) : 0.250ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: Hsync_sig_reg/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.385ns (logic 0.186ns (48.367%) route 0.199ns (51.633%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.783ns Source Clock Delay (SCD): -0.547ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.632 -0.547 clk_25MHz SLICE_X111Y30 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X111Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.406 f hor_cnt_reg[1]/Q net (fo=15, routed) 0.199 -0.207 hor_cnt_reg_n_0_[1] SLICE_X112Y31 LUT6 (Prop_lut6_I1_O) 0.045 -0.162 r Hsync_sig_i_2/O net (fo=2, routed) 0.000 -0.162 Hsync_sig SLICE_X112Y31 FDRE r Hsync_sig_reg/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.902 -0.783 clk_25MHz SLICE_X112Y31 FDRE r Hsync_sig_reg/C clock pessimism 0.251 -0.532 SLICE_X112Y31 FDRE (Hold_fdre_C_D) 0.120 -0.412 Hsync_sig_reg ------------------------------------------------------------------- required time 0.412 arrival time -0.162 ------------------------------------------------------------------- slack 0.250 Slack (MET) : 0.257ns (arrival time - required time) Source: out_reg_reg[5]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: out_reg_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.385ns (logic 0.186ns (48.340%) route 0.199ns (51.660%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.784ns Source Clock Delay (SCD): -0.547ns Clock Pessimism Removal (CPR): -0.273ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.632 -0.547 clk_25MHz SLICE_X110Y30 FDRE r out_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y30 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r out_reg_reg[5]/Q net (fo=1, routed) 0.199 -0.207 data1[4] SLICE_X109Y31 LUT5 (Prop_lut5_I0_O) 0.045 -0.162 r out_reg[4]_i_1/O net (fo=1, routed) 0.000 -0.162 out_reg[4] SLICE_X109Y31 FDRE r out_reg_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.901 -0.784 clk_25MHz SLICE_X109Y31 FDRE r out_reg_reg[4]/C clock pessimism 0.273 -0.511 SLICE_X109Y31 FDRE (Hold_fdre_C_D) 0.092 -0.419 out_reg_reg[4] ------------------------------------------------------------------- required time 0.419 arrival time -0.162 ------------------------------------------------------------------- slack 0.257 Slack (MET) : 0.258ns (arrival time - required time) Source: out_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[11]_lopt_replica_4/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100MHz_to_25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100MHz_to_25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100MHz_to_25MHz rise@0.000ns - clk_out_clk_100MHz_to_25MHz rise@0.000ns) Data Path Delay: 0.337ns (logic 0.141ns (41.866%) route 0.196ns (58.134%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.784ns Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.633 -0.546 clk_25MHz SLICE_X110Y31 FDRE r out_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X110Y31 FDRE (Prop_fdre_C_Q) 0.141 -0.405 r out_reg_reg[0]/Q net (fo=12, routed) 0.196 -0.209 out_reg_reg_n_0_[0] SLICE_X113Y30 FDRE r video_sig_reg[11]_lopt_replica_4/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100MHz_to_25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100MHz_to_25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100MHz_to_25MHz BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=45, routed) 0.901 -0.784 clk_25MHz SLICE_X113Y30 FDRE r video_sig_reg[11]_lopt_replica_4/C clock pessimism 0.251 -0.533 SLICE_X113Y30 FDRE (Hold_fdre_C_D) 0.066 -0.467 video_sig_reg[11]_lopt_replica_4 ------------------------------------------------------------------- required time 0.467 arrival time -0.209 ------------------------------------------------------------------- slack 0.258 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out_clk_100MHz_to_25MHz Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y0 clk_converter/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y31 A[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y31 A[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X113Y31 A[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y31 A[3]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X112Y31 Hsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X112Y28 Vsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X110Y29 hor_cnt_reg[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X111Y30 hor_cnt_reg[1]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y31 A[0]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y31 A[0]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y31 A[1]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y31 A[1]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y31 A[2]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y31 A[2]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y31 A[3]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y31 A[3]/C Low Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y31 Hsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y31 Hsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y28 Vsync_sig_reg/C High Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X112Y28 Vsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X110Y29 hor_cnt_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y29 hor_cnt_reg[7]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X113Y29 hor_cnt_reg[8]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X108Y31 out_reg_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y31 out_reg_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y31 out_reg_reg[3]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X109Y31 out_reg_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X111Y29 ver_cnt_reg[1]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_100MHz_to_25MHz To Clock: clkfbout_clk_100MHz_to_25MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_100MHz_to_25MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y1 clk_converter/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT