Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
| Date         : Fri Oct 27 11:18:27 2017
| Host         : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_control_sets -verbose -file chars_control_sets_placed.rpt
| Design       : chars
| Device       : xc7z020
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |     7 |
| Unused register locations in slices containing registers |    35 |
+----------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               2 |            2 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              25 |            9 |
| Yes          | No                    | No                     |               7 |            4 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |              11 |            4 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+-----------------------------+--------------------+--------------------+------------------+----------------+
|         Clock Signal        |    Enable Signal   |  Set/Reset Signal  | Slice Load Count | Bel Load Count |
+-----------------------------+--------------------+--------------------+------------------+----------------+
|  clk_converter/inst/clk_out | Vsync_sig          | Vsync_sig_i_1_n_0  |                1 |              1 |
|  clk_converter/inst/clk_out | Hsync_sig          | Hsync_sig_i_1_n_0  |                1 |              1 |
|  clk_converter/inst/clk_out |                    |                    |                2 |              2 |
|  clk_converter/inst/clk_out | out_reg[6]_i_1_n_0 |                    |                4 |              7 |
|  clk_converter/inst/clk_out | ver_cnt            | ver_cnt[9]_i_1_n_0 |                2 |              9 |
|  clk_converter/inst/clk_out |                    | p_0_in             |                5 |             12 |
|  clk_converter/inst/clk_out |                    | ver_cnt            |                4 |             13 |
+-----------------------------+--------------------+--------------------+------------------+----------------+


+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 1      |                     2 |
| 2      |                     1 |
| 7      |                     1 |
| 9      |                     1 |
| 12     |                     1 |
| 13     |                     1 |
+--------+-----------------------+