#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016
# IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
# Start of session at: Fri Oct 27 09:28:42 2017
# Process ID: 3817
# Current directory: /home/hakta/Documents/chars/chars.runs/clk_100MHz_to_25MHz_synth_1
# Command line: vivado -log clk_100MHz_to_25MHz.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_100MHz_to_25MHz.tcl
# Log file: /home/hakta/Documents/chars/chars.runs/clk_100MHz_to_25MHz_synth_1/clk_100MHz_to_25MHz.vds
# Journal file: /home/hakta/Documents/chars/chars.runs/clk_100MHz_to_25MHz_synth_1/vivado.jou
#-----------------------------------------------------------
source clk_100MHz_to_25MHz.tcl -notrace
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1084.969 ; gain = 157.082 ; free physical = 15791 ; free virtual = 17385
INFO: [Synth 8-638] synthesizing module 'clk_100MHz_to_25MHz' [/home/hakta/Documents/chars/chars.srcs/sources_1/ip/clk_100MHz_to_25MHz/clk_100MHz_to_25MHz.v:70]
INFO: [Synth 8-638] synthesizing module 'clk_100MHz_to_25MHz_clk_wiz' [/home/hakta/Documents/chars/chars.srcs/sources_1/ip/clk_100MHz_to_25MHz/clk_100MHz_to_25MHz_clk_wiz.v:68]
INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:14146]
INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:14146]
INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:20414]
INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:20414]
INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'clk_100MHz_to_25MHz_clk_wiz' (4#1) [/home/hakta/Documents/chars/chars.srcs/sources_1/ip/clk_100MHz_to_25MHz/clk_100MHz_to_25MHz_clk_wiz.v:68]
INFO: [Synth 8-256] done synthesizing module 'clk_100MHz_to_25MHz' (5#1) [/home/hakta/Documents/chars/chars.srcs/sources_1/ip/clk_100MHz_to_25MHz/clk_100MHz_to_25MHz.v:70]
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1126.445 ; gain = 198.559 ; free physical = 15746 ; free virtual = 17343
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1126.445 ; gain = 198.559 ; free physical = 15747 ; free virtual = 17344
INFO: [Device 21-403] Loading part xc7z020clg484-1
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1388.273 ; gain = 0.000 ; free physical = 15533 ; free virtual = 17156
Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1388.273 ; gain = 460.387 ; free physical = 15539 ; free virtual = 17153
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1388.273 ; gain = 460.387 ; free physical = 15539 ; free virtual = 17153
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1388.273 ; gain = 460.387 ; free physical = 15539 ; free virtual = 17153
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1388.273 ; gain = 460.387 ; free physical = 15539 ; free virtual = 17153
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1388.273 ; gain = 460.387 ; free physical = 15539 ; free virtual = 17153
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1411.273 ; gain = 483.387 ; free physical = 15503 ; free virtual = 17110
Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1411.273 ; gain = 483.387 ; free physical = 15503 ; free virtual = 17110
Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.285 ; gain = 492.398 ; free physical = 15495 ; free virtual = 17101
Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.289 ; gain = 492.402 ; free physical = 15495 ; free virtual = 17101
Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.289 ; gain = 492.402 ; free physical = 15495 ; free virtual = 17101
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.289 ; gain = 492.402 ; free physical = 15495 ; free virtual = 17101
Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.289 ; gain = 492.402 ; free physical = 15495 ; free virtual = 17101
Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.289 ; gain = 492.402 ; free physical = 15495 ; free virtual = 17101
Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.289 ; gain = 492.402 ; free physical = 15495 ; free virtual = 17101

Report Cell Usage: 
+------+-----------+------+
|      |Cell       |Count |
+------+-----------+------+
|1     |BUFG       |     2|
|2     |MMCME2_ADV |     1|
|3     |IBUF       |     1|
+------+-----------+------+
Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1420.289 ; gain = 492.402 ; free physical = 15495 ; free virtual = 17101
synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1754.434 ; gain = 751.043 ; free physical = 15155 ; free virtual = 16779