#----------------------------------------------------------- # Vivado v2016.4 (64-bit) # SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016 # IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016 # Start of session at: Wed Dec 13 11:57:35 2017 # Process ID: 16445 # Current directory: /home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1 # Command line: vivado -log blockout.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source blockout.tcl # Log file: /home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/blockout.vds # Journal file: /home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/vivado.jou #----------------------------------------------------------- source blockout.tcl -notrace Command: synth_design -top blockout -part xc7z020clg484-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16450 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1086.977 ; gain = 159.082 ; free physical = 15450 ; free virtual = 17076 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'blockout' [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:20] INFO: [Synth 8-3491] module 'clk_100to25MHz' declared at '/home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/.Xil/Vivado-16445-VLSI-01/realtime/clk_100to25MHz_stub.vhdl:5' bound to instance 'clk_converter' of component 'clk_100to25MHz' [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:244] INFO: [Synth 8-638] synthesizing module 'clk_100to25MHz' [/home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/.Xil/Vivado-16445-VLSI-01/realtime/clk_100to25MHz_stub.vhdl:13] INFO: [Synth 8-256] done synthesizing module 'blockout' (1#1) [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:20] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1153.453 ; gain = 225.559 ; free physical = 15383 ; free virtual = 17010 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1153.453 ; gain = 225.559 ; free physical = 15382 ; free virtual = 17009 --------------------------------------------------------------------------------- WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'clk_100to25MHz' instantiated as 'clk_converter' [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:244] INFO: [Device 21-403] Loading part xc7z020clg484-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/.Xil/Vivado-16445-VLSI-01/dcp/clk_100to25MHz_in_context.xdc] for cell 'clk_converter' Finished Parsing XDC File [/home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/.Xil/Vivado-16445-VLSI-01/dcp/clk_100to25MHz_in_context.xdc] for cell 'clk_converter' Parsing XDC File [/home/hakta/Documents/FPGA/blockout/blockout.srcs/constrs_1/new/blockout.xdc] WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 33]]'. [/home/hakta/Documents/FPGA/blockout/blockout.srcs/constrs_1/new/blockout.xdc:39] WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 34]]'. [/home/hakta/Documents/FPGA/blockout/blockout.srcs/constrs_1/new/blockout.xdc:44] WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 35]]'. [/home/hakta/Documents/FPGA/blockout/blockout.srcs/constrs_1/new/blockout.xdc:49] WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 13]]'. [/home/hakta/Documents/FPGA/blockout/blockout.srcs/constrs_1/new/blockout.xdc:52] Finished Parsing XDC File [/home/hakta/Documents/FPGA/blockout/blockout.srcs/constrs_1/new/blockout.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/hakta/Documents/FPGA/blockout/blockout.srcs/constrs_1/new/blockout.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/blockout_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/blockout_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1500.805 ; gain = 0.004 ; free physical = 15100 ; free virtual = 16726 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1500.805 ; gain = 572.910 ; free physical = 15101 ; free virtual = 16727 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg484-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1500.805 ; gain = 572.910 ; free physical = 15101 ; free virtual = 16727 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property IO_BUFFER_TYPE = NONE for clk_100MHz. (constraint file /home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/.Xil/Vivado-16445-VLSI-01/dcp/clk_100to25MHz_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for clk_100MHz. (constraint file /home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/.Xil/Vivado-16445-VLSI-01/dcp/clk_100to25MHz_in_context.xdc, line 4). Applied set_property DONT_TOUCH = true for clk_converter. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1500.805 ; gain = 572.910 ; free physical = 15101 ; free virtual = 16727 --------------------------------------------------------------------------------- INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:341] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:341] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:311] INFO: [Synth 8-5818] HDL ADVISOR - The operator resource is shared. To prevent sharing consider applying a KEEP on the output of the operator [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:311] INFO: [Synth 8-5546] ROM "ver_cnt" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "enable" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5545] ROM "matrix_reg[0,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1500.805 ; gain = 572.910 ; free physical = 15110 ; free virtual = 16725 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 2 2 Input 10 Bit Adders := 2 3 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 4 2 Input 2 Bit Adders := 4 +---Registers : 13 Bit Registers := 4 12 Bit Registers := 1 10 Bit Registers := 3 2 Bit Registers := 64 1 Bit Registers := 3 +---Muxes : 2 Input 13 Bit Muxes := 6 2 Input 12 Bit Muxes := 1 2 Input 2 Bit Muxes := 401 2 Input 1 Bit Muxes := 659 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module blockout Detailed RTL Component Info : +---Adders : 2 Input 13 Bit Adders := 2 2 Input 10 Bit Adders := 2 3 Input 10 Bit Adders := 1 2 Input 9 Bit Adders := 4 2 Input 2 Bit Adders := 4 +---Registers : 13 Bit Registers := 4 12 Bit Registers := 1 10 Bit Registers := 3 2 Bit Registers := 64 1 Bit Registers := 3 +---Muxes : 2 Input 13 Bit Muxes := 6 2 Input 12 Bit Muxes := 1 2 Input 2 Bit Muxes := 401 2 Input 1 Bit Muxes := 659 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-4471] merging register 'hor_cnt_reg[9:0]' into 'hor_cnt_reg[9:0]' [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/new/blockout.vhd:253] INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "ver_cnt" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5545] ROM "matrix_reg[0,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5546] ROM "enable" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5545] ROM "matrix_reg[3,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[1,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[2,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[3,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[4,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[5,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[6,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[7,1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "matrix_reg[0,2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Common 17-14] Message 'Synth 8-5545' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 1500.809 ; gain = 572.914 ; free physical = 15099 ; free virtual = 16713 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: +------------+------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+------------+---------------+----------------+ |blockout | ghost[0] | 1024x12 | LUT | |blockout | ghost[0] | 1024x12 | LUT | +------------+------------+---------------+----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- INFO: [Synth 8-5578] Moved timing constraint from pin 'clk_converter/clk_out' to pin 'clk_converter/bbstub_clk_out/O' INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1500.809 ; gain = 572.914 ; free physical = 15097 ; free virtual = 16711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:52 ; elapsed = 00:00:52 . Memory (MB): peak = 1570.426 ; gain = 642.531 ; free physical = 15037 ; free virtual = 16652 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-3886] merging instance 'video_sig_reg[3]' (FDR) to 'video_sig_reg[7]' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:52 ; elapsed = 00:00:53 . Memory (MB): peak = 1586.441 ; gain = 658.547 ; free physical = 15027 ; free virtual = 16641 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:53 ; elapsed = 00:00:53 . Memory (MB): peak = 1586.445 ; gain = 658.551 ; free physical = 15027 ; free virtual = 16642 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:53 ; elapsed = 00:00:53 . Memory (MB): peak = 1586.445 ; gain = 658.551 ; free physical = 15027 ; free virtual = 16642 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:53 ; elapsed = 00:00:53 . Memory (MB): peak = 1586.445 ; gain = 658.551 ; free physical = 15027 ; free virtual = 16642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:53 ; elapsed = 00:00:53 . Memory (MB): peak = 1586.445 ; gain = 658.551 ; free physical = 15027 ; free virtual = 16642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 1586.445 ; gain = 658.551 ; free physical = 15027 ; free virtual = 16642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 1586.445 ; gain = 658.551 ; free physical = 15027 ; free virtual = 16642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+---------------+----------+ | |BlackBox name |Instances | +------+---------------+----------+ |1 |clk_100to25MHz | 1| +------+---------------+----------+ Report Cell Usage: +------+--------------------+------+ | |Cell |Count | +------+--------------------+------+ |1 |clk_100to25MHz_bbox | 1| |2 |BUFG | 1| |3 |CARRY4 | 35| |4 |LUT1 | 30| |5 |LUT2 | 64| |6 |LUT3 | 57| |7 |LUT4 | 93| |8 |LUT5 | 146| |9 |LUT6 | 700| |10 |MUXF7 | 49| |11 |MUXF8 | 10| |12 |FDRE | 214| |13 |OBUF | 14| +------+--------------------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1414| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 1586.445 ; gain = 658.551 ; free physical = 15027 ; free virtual = 16642 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1586.445 ; gain = 218.113 ; free physical = 15027 ; free virtual = 16642 Synthesis Optimization Complete : Time (s): cpu = 00:00:53 ; elapsed = 00:00:54 . Memory (MB): peak = 1586.449 ; gain = 658.555 ; free physical = 15027 ; free virtual = 16642 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 35 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'blockout' is not ideal for floorplanning, since the cellview 'blockout' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 138 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:00:52 . Memory (MB): peak = 1586.449 ; gain = 582.051 ; free physical = 15030 ; free virtual = 16644 INFO: [Common 17-1381] The checkpoint '/home/hakta/Documents/FPGA/blockout/blockout.runs/synth_1/blockout.dcp' has been generated. report_utilization: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1610.457 ; gain = 0.000 ; free physical = 15026 ; free virtual = 16641 INFO: [Common 17-206] Exiting Vivado at Wed Dec 13 11:58:35 2017...