Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016 | Date : Wed Dec 13 11:59:20 2017 | Host : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS | Command : report_timing_summary -warn_on_violation -max_paths 10 -file blockout_timing_summary_routed.rpt -rpx blockout_timing_summary_routed.rpx | Design : blockout | Device : 7z020-clg484 | Speed File : -1 PRODUCTION 1.11 2014-09-11 --------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 180 register/latch pins with no clock driven by root clock pin: enable_reg/Q (HIGH) 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 232 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 0 input ports with no input delay specified. There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 14 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 29.928 0.000 0 61 0.091 0.000 0 61 3.000 0.000 0 41 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk_100MHz {0.000 5.000} 10.000 100.000 clk_out_clk_100to25MHz {0.000 20.000} 40.000 25.000 clkfbout_clk_100to25MHz {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk_100MHz 3.000 0.000 0 1 clk_out_clk_100to25MHz 29.928 0.000 0 61 0.091 0.000 0 61 19.500 0.000 0 37 clkfbout_clk_100to25MHz 7.845 0.000 0 3 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk_100MHz To Clock: clk_100MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100MHz } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_out_clk_100to25MHz To Clock: clk_out_clk_100to25MHz Setup : 0 Failing Endpoints, Worst Slack 29.928ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.091ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 29.928ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[5]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 9.931ns (logic 3.710ns (37.357%) route 6.221ns (62.643%)) Logic Levels: 12 (CARRY4=4 LUT2=2 LUT3=1 LUT5=2 LUT6=2 MUXF7=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.593ns = ( 38.407 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 f video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 1.814 5.765 ghost[0]1[8] SLICE_X46Y47 LUT6 (Prop_lut6_I0_O) 0.299 6.064 r video_sig[5]_i_12/O net (fo=1, routed) 0.000 6.064 video_sig[5]_i_12_n_0 SLICE_X46Y47 MUXF7 (Prop_muxf7_I1_O) 0.214 6.278 r video_sig_reg[5]_i_5/O net (fo=2, routed) 0.893 7.171 video_sig_reg[5]_i_5_n_0 SLICE_X46Y47 LUT5 (Prop_lut5_I0_O) 0.297 7.468 r video_sig[5]_i_3/O net (fo=1, routed) 0.407 7.876 video_sig[5]_i_3_n_0 SLICE_X47Y47 LUT6 (Prop_lut6_I1_O) 0.124 8.000 r video_sig[5]_i_2/O net (fo=1, routed) 0.814 8.814 video_sig[5]_i_2_n_0 SLICE_X50Y47 LUT3 (Prop_lut3_I0_O) 0.148 8.962 r video_sig[5]_i_1/O net (fo=1, routed) 0.000 8.962 video_sig[5]_i_1_n_0 SLICE_X50Y47 FDRE r video_sig_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.480 38.407 clk_25MHz SLICE_X50Y47 FDRE r video_sig_reg[5]/C clock pessimism 0.462 38.869 clock uncertainty -0.098 38.771 SLICE_X50Y47 FDRE (Setup_fdre_C_D) 0.118 38.889 video_sig_reg[5] ------------------------------------------------------------------- required time 38.889 arrival time -8.962 ------------------------------------------------------------------- slack 29.928 Slack (MET) : 30.146ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 9.669ns (logic 3.712ns (38.390%) route 5.957ns (61.610%)) Logic Levels: 12 (CARRY4=4 LUT2=2 LUT3=1 LUT5=2 LUT6=2 MUXF7=1) Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.594ns = ( 38.406 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 f video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 1.814 5.765 ghost[0]1[8] SLICE_X46Y47 LUT6 (Prop_lut6_I0_O) 0.299 6.064 r video_sig[5]_i_12/O net (fo=1, routed) 0.000 6.064 video_sig[5]_i_12_n_0 SLICE_X46Y47 MUXF7 (Prop_muxf7_I1_O) 0.214 6.278 r video_sig_reg[5]_i_5/O net (fo=2, routed) 0.358 6.636 video_sig_reg[5]_i_5_n_0 SLICE_X47Y47 LUT5 (Prop_lut5_I0_O) 0.297 6.933 r video_sig[1]_i_3/O net (fo=1, routed) 0.665 7.598 video_sig[1]_i_3_n_0 SLICE_X47Y47 LUT6 (Prop_lut6_I1_O) 0.124 7.722 r video_sig[1]_i_2/O net (fo=1, routed) 0.827 8.550 video_sig[1]_i_2_n_0 SLICE_X52Y46 LUT3 (Prop_lut3_I0_O) 0.150 8.700 r video_sig[1]_i_1/O net (fo=1, routed) 0.000 8.700 video_sig[1]_i_1_n_0 SLICE_X52Y46 FDRE r video_sig_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.479 38.406 clk_25MHz SLICE_X52Y46 FDRE r video_sig_reg[1]/C clock pessimism 0.462 38.868 clock uncertainty -0.098 38.770 SLICE_X52Y46 FDRE (Setup_fdre_C_D) 0.075 38.845 video_sig_reg[1] ------------------------------------------------------------------- required time 38.845 arrival time -8.700 ------------------------------------------------------------------- slack 30.146 Slack (MET) : 30.568ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[6]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 9.259ns (logic 3.327ns (35.932%) route 5.932ns (64.068%)) Logic Levels: 11 (CARRY4=4 LUT2=2 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.582ns = ( 38.418 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 r video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 1.226 5.178 ghost[0]1[8] SLICE_X44Y48 LUT6 (Prop_lut6_I0_O) 0.299 5.477 r video_sig[10]_i_12/O net (fo=1, routed) 0.706 6.183 video_sig[10]_i_12_n_0 SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.124 6.307 r video_sig[10]_i_5/O net (fo=3, routed) 1.032 7.339 video_sig[10]_i_5_n_0 SLICE_X48Y48 LUT6 (Prop_lut6_I3_O) 0.124 7.463 r video_sig[6]_i_2/O net (fo=1, routed) 0.674 8.137 video_sig[6]_i_2_n_0 SLICE_X48Y48 LUT3 (Prop_lut3_I0_O) 0.152 8.289 r video_sig[6]_i_1/O net (fo=1, routed) 0.000 8.289 video_sig[6]_i_1_n_0 SLICE_X48Y48 FDRE r video_sig_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.491 38.418 clk_25MHz SLICE_X48Y48 FDRE r video_sig_reg[6]/C clock pessimism 0.462 38.880 clock uncertainty -0.098 38.782 SLICE_X48Y48 FDRE (Setup_fdre_C_D) 0.075 38.857 video_sig_reg[6] ------------------------------------------------------------------- required time 38.857 arrival time -8.289 ------------------------------------------------------------------- slack 30.568 Slack (MET) : 30.640ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 9.029ns (logic 3.691ns (40.877%) route 5.338ns (59.123%)) Logic Levels: 12 (CARRY4=4 LUT2=2 LUT5=4 LUT6=1 MUXF7=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.583ns = ( 38.417 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 f video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 0.549 4.500 ghost[0]1[8] SLICE_X45Y51 LUT5 (Prop_lut5_I0_O) 0.299 4.799 r video_sig[11]_i_104/O net (fo=1, routed) 0.000 4.799 video_sig[11]_i_104_n_0 SLICE_X45Y51 MUXF7 (Prop_muxf7_I1_O) 0.217 5.016 r video_sig_reg[11]_i_77/O net (fo=1, routed) 0.354 5.371 video_sig_reg[11]_i_77_n_0 SLICE_X44Y51 LUT6 (Prop_lut6_I5_O) 0.299 5.670 r video_sig[11]_i_26/O net (fo=2, routed) 0.425 6.094 video_sig[11]_i_26_n_0 SLICE_X44Y50 LUT5 (Prop_lut5_I0_O) 0.124 6.218 r video_sig[7]_i_2/O net (fo=1, routed) 0.954 7.173 video_sig[7]_i_2_n_0 SLICE_X49Y49 LUT5 (Prop_lut5_I0_O) 0.124 7.297 r video_sig[7]_i_1/O net (fo=2, routed) 0.763 8.060 video_sig[7]_i_1_n_0 SLICE_X49Y46 FDRE r video_sig_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.490 38.417 clk_25MHz SLICE_X49Y46 FDRE r video_sig_reg[7]/C clock pessimism 0.462 38.879 clock uncertainty -0.098 38.781 SLICE_X49Y46 FDRE (Setup_fdre_C_D) -0.081 38.700 video_sig_reg[7] ------------------------------------------------------------------- required time 38.700 arrival time -8.060 ------------------------------------------------------------------- slack 30.640 Slack (MET) : 30.741ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 9.040ns (logic 3.299ns (36.495%) route 5.741ns (63.505%)) Logic Levels: 11 (CARRY4=4 LUT2=2 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.151ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.582ns = ( 38.418 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 r video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 1.226 5.178 ghost[0]1[8] SLICE_X44Y48 LUT6 (Prop_lut6_I0_O) 0.299 5.477 r video_sig[10]_i_12/O net (fo=1, routed) 0.706 6.183 video_sig[10]_i_12_n_0 SLICE_X45Y48 LUT6 (Prop_lut6_I1_O) 0.124 6.307 r video_sig[10]_i_5/O net (fo=3, routed) 1.031 7.338 video_sig[10]_i_5_n_0 SLICE_X48Y48 LUT6 (Prop_lut6_I3_O) 0.124 7.462 r video_sig[2]_i_2/O net (fo=1, routed) 0.484 7.946 video_sig[2]_i_2_n_0 SLICE_X48Y48 LUT3 (Prop_lut3_I0_O) 0.124 8.070 r video_sig[2]_i_1/O net (fo=1, routed) 0.000 8.070 video_sig[2]_i_1_n_0 SLICE_X48Y48 FDRE r video_sig_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.491 38.418 clk_25MHz SLICE_X48Y48 FDRE r video_sig_reg[2]/C clock pessimism 0.462 38.880 clock uncertainty -0.098 38.782 SLICE_X48Y48 FDRE (Setup_fdre_C_D) 0.029 38.811 video_sig_reg[2] ------------------------------------------------------------------- required time 38.811 arrival time -8.070 ------------------------------------------------------------------- slack 30.741 Slack (MET) : 30.755ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 9.025ns (logic 3.691ns (40.899%) route 5.334ns (59.101%)) Logic Levels: 12 (CARRY4=4 LUT2=2 LUT3=1 LUT5=2 LUT6=2 MUXF7=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.583ns = ( 38.417 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 f video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 0.950 4.902 ghost[0]1[8] SLICE_X44Y48 LUT6 (Prop_lut6_I0_O) 0.299 5.201 r video_sig[8]_i_22/O net (fo=1, routed) 0.000 5.201 video_sig[8]_i_22_n_0 SLICE_X44Y48 MUXF7 (Prop_muxf7_I1_O) 0.217 5.418 r video_sig_reg[8]_i_13/O net (fo=2, routed) 0.658 6.076 video_sig_reg[8]_i_13_n_0 SLICE_X45Y47 LUT5 (Prop_lut5_I0_O) 0.299 6.375 r video_sig[4]_i_4/O net (fo=2, routed) 0.963 7.338 video_sig[4]_i_4_n_0 SLICE_X49Y46 LUT6 (Prop_lut6_I3_O) 0.124 7.462 r video_sig[4]_i_2/O net (fo=1, routed) 0.469 7.931 video_sig[4]_i_2_n_0 SLICE_X49Y46 LUT3 (Prop_lut3_I0_O) 0.124 8.055 r video_sig[4]_i_1/O net (fo=1, routed) 0.000 8.055 video_sig[4]_i_1_n_0 SLICE_X49Y46 FDRE r video_sig_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.490 38.417 clk_25MHz SLICE_X49Y46 FDRE r video_sig_reg[4]/C clock pessimism 0.462 38.879 clock uncertainty -0.098 38.781 SLICE_X49Y46 FDRE (Setup_fdre_C_D) 0.029 38.810 video_sig_reg[4] ------------------------------------------------------------------- required time 38.810 arrival time -8.055 ------------------------------------------------------------------- slack 30.755 Slack (MET) : 30.783ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[10]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 9.035ns (logic 3.691ns (40.853%) route 5.344ns (59.147%)) Logic Levels: 12 (CARRY4=4 LUT2=2 LUT3=1 LUT5=1 LUT6=3 MUXF7=1) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.593ns = ( 38.407 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 f video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 0.553 4.505 ghost[0]1[8] SLICE_X43Y51 LUT6 (Prop_lut6_I0_O) 0.299 4.804 r video_sig[10]_i_18/O net (fo=1, routed) 0.000 4.804 video_sig[10]_i_18_n_0 SLICE_X43Y51 MUXF7 (Prop_muxf7_I1_O) 0.217 5.021 r video_sig_reg[10]_i_8/O net (fo=1, routed) 0.808 5.829 video_sig_reg[10]_i_8_n_0 SLICE_X44Y51 LUT6 (Prop_lut6_I5_O) 0.299 6.128 r video_sig[10]_i_3/O net (fo=3, routed) 1.123 7.251 video_sig[10]_i_3_n_0 SLICE_X48Y48 LUT6 (Prop_lut6_I0_O) 0.124 7.375 r video_sig[10]_i_2/O net (fo=1, routed) 0.566 7.941 video_sig[10]_i_2_n_0 SLICE_X50Y47 LUT3 (Prop_lut3_I0_O) 0.124 8.065 r video_sig[10]_i_1/O net (fo=1, routed) 0.000 8.065 video_sig[10]_i_1_n_0 SLICE_X50Y47 FDRE r video_sig_reg[10]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.480 38.407 clk_25MHz SLICE_X50Y47 FDRE r video_sig_reg[10]/C clock pessimism 0.462 38.869 clock uncertainty -0.098 38.771 SLICE_X50Y47 FDRE (Setup_fdre_C_D) 0.077 38.848 video_sig_reg[10] ------------------------------------------------------------------- required time 38.848 arrival time -8.065 ------------------------------------------------------------------- slack 30.783 Slack (MET) : 30.787ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[7]_lopt_replica/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 8.903ns (logic 3.691ns (41.459%) route 5.212ns (58.541%)) Logic Levels: 12 (CARRY4=4 LUT2=2 LUT5=4 LUT6=1 MUXF7=1) Clock Path Skew: -0.152ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.583ns = ( 38.417 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 f video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 0.549 4.500 ghost[0]1[8] SLICE_X45Y51 LUT5 (Prop_lut5_I0_O) 0.299 4.799 r video_sig[11]_i_104/O net (fo=1, routed) 0.000 4.799 video_sig[11]_i_104_n_0 SLICE_X45Y51 MUXF7 (Prop_muxf7_I1_O) 0.217 5.016 r video_sig_reg[11]_i_77/O net (fo=1, routed) 0.354 5.371 video_sig_reg[11]_i_77_n_0 SLICE_X44Y51 LUT6 (Prop_lut6_I5_O) 0.299 5.670 r video_sig[11]_i_26/O net (fo=2, routed) 0.425 6.094 video_sig[11]_i_26_n_0 SLICE_X44Y50 LUT5 (Prop_lut5_I0_O) 0.124 6.218 r video_sig[7]_i_2/O net (fo=1, routed) 0.954 7.173 video_sig[7]_i_2_n_0 SLICE_X49Y49 LUT5 (Prop_lut5_I0_O) 0.124 7.297 r video_sig[7]_i_1/O net (fo=2, routed) 0.636 7.933 video_sig[7]_i_1_n_0 SLICE_X49Y46 FDRE r video_sig_reg[7]_lopt_replica/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.490 38.417 clk_25MHz SLICE_X49Y46 FDRE r video_sig_reg[7]_lopt_replica/C clock pessimism 0.462 38.879 clock uncertainty -0.098 38.781 SLICE_X49Y46 FDRE (Setup_fdre_C_D) -0.061 38.720 video_sig_reg[7]_lopt_replica ------------------------------------------------------------------- required time 38.720 arrival time -7.933 ------------------------------------------------------------------- slack 30.787 Slack (MET) : 30.879ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 8.890ns (logic 3.299ns (37.109%) route 5.591ns (62.891%)) Logic Levels: 11 (CARRY4=4 LUT2=2 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.163ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.594ns = ( 38.406 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 r video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 1.698 5.650 ghost[0]1[8] SLICE_X50Y46 LUT6 (Prop_lut6_I0_O) 0.299 5.949 r video_sig[0]_i_6/O net (fo=1, routed) 0.452 6.401 video_sig[0]_i_6_n_0 SLICE_X50Y46 LUT6 (Prop_lut6_I0_O) 0.124 6.525 r video_sig[0]_i_4/O net (fo=1, routed) 0.587 7.112 video_sig[0]_i_4_n_0 SLICE_X49Y46 LUT6 (Prop_lut6_I5_O) 0.124 7.236 r video_sig[0]_i_2/O net (fo=1, routed) 0.561 7.796 video_sig[0]_i_2_n_0 SLICE_X52Y46 LUT3 (Prop_lut3_I0_O) 0.124 7.920 r video_sig[0]_i_1/O net (fo=1, routed) 0.000 7.920 video_sig[0]_i_1_n_0 SLICE_X52Y46 FDRE r video_sig_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.479 38.406 clk_25MHz SLICE_X52Y46 FDRE r video_sig_reg[0]/C clock pessimism 0.462 38.868 clock uncertainty -0.098 38.770 SLICE_X52Y46 FDRE (Setup_fdre_C_D) 0.029 38.799 video_sig_reg[0] ------------------------------------------------------------------- required time 38.799 arrival time -7.920 ------------------------------------------------------------------- slack 30.879 Slack (MET) : 30.881ns (required time - arrival time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: video_sig_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Setup (Max at Slow Process Corner) Requirement: 40.000ns (clk_out_clk_100to25MHz rise@40.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 8.941ns (logic 3.299ns (36.898%) route 5.642ns (63.102%)) Logic Levels: 11 (CARRY4=4 LUT2=2 LUT3=1 LUT5=1 LUT6=3) Clock Path Skew: -0.162ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.593ns = ( 38.407 - 40.000 ) Source Clock Delay (SCD): -0.970ns Clock Pessimism Removal (CPR): 0.462ns Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.182ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.490 1.490 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.285 2.775 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.343 -4.568 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.855 -2.713 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.101 -2.612 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.642 -0.970 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.456 -0.514 r ver_cnt_reg[0]/Q net (fo=21, routed) 1.318 0.804 ver_cnt_reg_n_0_[0] SLICE_X47Y56 LUT2 (Prop_lut2_I0_O) 0.124 0.928 r video_sig[11]_i_116/O net (fo=1, routed) 0.000 0.928 video_sig[11]_i_116_n_0 SLICE_X47Y56 CARRY4 (Prop_carry4_S[0]_O[0]) 0.247 1.175 r video_sig_reg[11]_i_107/O[0] net (fo=1, routed) 0.296 1.471 A[0] SLICE_X47Y54 LUT2 (Prop_lut2_I1_O) 0.299 1.770 r video_sig[11]_i_92/O net (fo=1, routed) 0.000 1.770 video_sig[11]_i_92_n_0 SLICE_X47Y54 CARRY4 (Prop_carry4_S[1]_O[2]) 0.580 2.350 r video_sig_reg[11]_i_31/O[2] net (fo=2, routed) 0.680 3.030 PCOUT[6] SLICE_X47Y52 LUT5 (Prop_lut5_I4_O) 0.302 3.332 r video_sig[11]_i_33/O net (fo=1, routed) 0.000 3.332 video_sig[11]_i_33_n_0 SLICE_X47Y52 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.398 3.730 r video_sig_reg[11]_i_9/CO[3] net (fo=1, routed) 0.000 3.730 video_sig_reg[11]_i_9_n_0 SLICE_X47Y53 CARRY4 (Prop_carry4_CI_O[0]) 0.222 3.952 f video_sig_reg[11]_i_27/O[0] net (fo=92, routed) 1.469 5.421 ghost[0]1[8] SLICE_X46Y49 LUT6 (Prop_lut6_I0_O) 0.299 5.720 r video_sig[9]_i_7/O net (fo=1, routed) 0.452 6.172 video_sig[9]_i_7_n_0 SLICE_X46Y49 LUT6 (Prop_lut6_I0_O) 0.124 6.296 r video_sig[9]_i_3/O net (fo=3, routed) 0.670 6.966 video_sig[9]_i_3_n_0 SLICE_X46Y48 LUT6 (Prop_lut6_I0_O) 0.124 7.090 r video_sig[9]_i_2/O net (fo=1, routed) 0.757 7.847 video_sig[9]_i_2_n_0 SLICE_X50Y47 LUT3 (Prop_lut3_I0_O) 0.124 7.971 r video_sig[9]_i_1/O net (fo=1, routed) 0.000 7.971 video_sig[9]_i_1_n_0 SLICE_X50Y47 FDRE r video_sig_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 40.000 40.000 r Y9 0.000 40.000 r clk_100MHz (IN) net (fo=0) 0.000 40.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 1.420 41.420 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 1.162 42.582 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -7.438 35.144 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 1.691 36.835 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.091 36.926 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 1.480 38.407 clk_25MHz SLICE_X50Y47 FDRE r video_sig_reg[9]/C clock pessimism 0.462 38.869 clock uncertainty -0.098 38.771 SLICE_X50Y47 FDRE (Setup_fdre_C_D) 0.081 38.852 video_sig_reg[9] ------------------------------------------------------------------- required time 38.852 arrival time -7.971 ------------------------------------------------------------------- slack 30.881 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.091ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.471ns (logic 0.227ns (48.174%) route 0.244ns (51.826%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.260ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.622ns Clock Pessimism Removal (CPR): -0.502ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.557 -0.622 clk_25MHz SLICE_X48Y53 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y53 FDRE (Prop_fdre_C_Q) 0.128 -0.494 r hor_cnt_reg[1]/Q net (fo=14, routed) 0.244 -0.249 hor_cnt_reg_n_0_[1] SLICE_X50Y53 LUT5 (Prop_lut5_I4_O) 0.099 -0.150 r hor_cnt[4]_i_1/O net (fo=1, routed) 0.000 -0.150 hor_cnt[4] SLICE_X50Y53 FDRE r hor_cnt_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X50Y53 FDRE r hor_cnt_reg[4]/C clock pessimism 0.502 -0.361 SLICE_X50Y53 FDRE (Hold_fdre_C_D) 0.120 -0.241 hor_cnt_reg[4] ------------------------------------------------------------------- required time 0.241 arrival time -0.150 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.179ns (arrival time - required time) Source: hor_cnt_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.313ns (logic 0.186ns (59.512%) route 0.127ns (40.488%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.625ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.554 -0.625 clk_25MHz SLICE_X51Y53 FDRE r hor_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y53 FDRE (Prop_fdre_C_Q) 0.141 -0.484 r hor_cnt_reg[7]/Q net (fo=14, routed) 0.127 -0.357 hor_cnt_reg_n_0_[7] SLICE_X50Y53 LUT6 (Prop_lut6_I3_O) 0.045 -0.312 r hor_cnt[8]_i_1/O net (fo=1, routed) 0.000 -0.312 hor_cnt[8] SLICE_X50Y53 FDRE r hor_cnt_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X50Y53 FDRE r hor_cnt_reg[8]/C clock pessimism 0.251 -0.612 SLICE_X50Y53 FDRE (Hold_fdre_C_D) 0.121 -0.491 hor_cnt_reg[8] ------------------------------------------------------------------- required time 0.491 arrival time -0.312 ------------------------------------------------------------------- slack 0.179 Slack (MET) : 0.186ns (arrival time - required time) Source: ver_cnt_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: enable_reg/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.290ns (logic 0.186ns (64.199%) route 0.104ns (35.801%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.625ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.554 -0.625 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.484 f ver_cnt_reg[0]/Q net (fo=21, routed) 0.104 -0.380 ver_cnt_reg_n_0_[0] SLICE_X52Y54 LUT6 (Prop_lut6_I1_O) 0.045 -0.335 r enable_i_1/O net (fo=1, routed) 0.000 -0.335 enable_i_1_n_0 SLICE_X52Y54 FDRE r enable_reg/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X52Y54 FDRE r enable_reg/C clock pessimism 0.251 -0.612 SLICE_X52Y54 FDRE (Hold_fdre_C_D) 0.091 -0.521 enable_reg ------------------------------------------------------------------- required time 0.521 arrival time -0.335 ------------------------------------------------------------------- slack 0.186 Slack (MET) : 0.210ns (arrival time - required time) Source: ver_cnt_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.343ns (logic 0.186ns (54.278%) route 0.157ns (45.722%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.625ns Clock Pessimism Removal (CPR): -0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.554 -0.625 clk_25MHz SLICE_X51Y55 FDRE r ver_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y55 FDRE (Prop_fdre_C_Q) 0.141 -0.484 r ver_cnt_reg[3]/Q net (fo=21, routed) 0.157 -0.327 ver_cnt_reg_n_0_[3] SLICE_X50Y55 LUT5 (Prop_lut5_I2_O) 0.045 -0.282 r ver_cnt[4]_i_1/O net (fo=1, routed) 0.000 -0.282 ver_cnt[4]_i_1_n_0 SLICE_X50Y55 FDRE r ver_cnt_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X50Y55 FDRE r ver_cnt_reg[4]/C clock pessimism 0.251 -0.612 SLICE_X50Y55 FDRE (Hold_fdre_C_D) 0.120 -0.492 ver_cnt_reg[4] ------------------------------------------------------------------- required time 0.492 arrival time -0.282 ------------------------------------------------------------------- slack 0.210 Slack (MET) : 0.219ns (arrival time - required time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[6]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.326ns (logic 0.186ns (57.128%) route 0.140ns (42.872%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.625ns Clock Pessimism Removal (CPR): -0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.554 -0.625 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.484 r ver_cnt_reg[1]/Q net (fo=21, routed) 0.140 -0.344 ver_cnt_reg_n_0_[1] SLICE_X51Y54 LUT6 (Prop_lut6_I5_O) 0.045 -0.299 r ver_cnt[6]_i_1/O net (fo=1, routed) 0.000 -0.299 ver_cnt[6]_i_1_n_0 SLICE_X51Y54 FDRE r ver_cnt_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X51Y54 FDRE r ver_cnt_reg[6]/C clock pessimism 0.254 -0.609 SLICE_X51Y54 FDRE (Hold_fdre_C_D) 0.091 -0.518 ver_cnt_reg[6] ------------------------------------------------------------------- required time 0.518 arrival time -0.299 ------------------------------------------------------------------- slack 0.219 Slack (MET) : 0.224ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[3]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.615ns (logic 0.226ns (36.718%) route 0.389ns (63.282%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.260ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.622ns Clock Pessimism Removal (CPR): -0.502ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.557 -0.622 clk_25MHz SLICE_X48Y53 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y53 FDRE (Prop_fdre_C_Q) 0.128 -0.494 r hor_cnt_reg[1]/Q net (fo=14, routed) 0.389 -0.104 hor_cnt_reg_n_0_[1] SLICE_X50Y54 LUT4 (Prop_lut4_I2_O) 0.098 -0.006 r hor_cnt[3]_i_1/O net (fo=1, routed) 0.000 -0.006 hor_cnt[3] SLICE_X50Y54 FDRE r hor_cnt_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X50Y54 FDRE r hor_cnt_reg[3]/C clock pessimism 0.502 -0.361 SLICE_X50Y54 FDRE (Hold_fdre_C_D) 0.131 -0.230 hor_cnt_reg[3] ------------------------------------------------------------------- required time 0.230 arrival time -0.006 ------------------------------------------------------------------- slack 0.224 Slack (MET) : 0.236ns (arrival time - required time) Source: hor_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[2]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.616ns (logic 0.227ns (36.821%) route 0.389ns (63.179%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.260ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.622ns Clock Pessimism Removal (CPR): -0.502ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.557 -0.622 clk_25MHz SLICE_X48Y53 FDRE r hor_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y53 FDRE (Prop_fdre_C_Q) 0.128 -0.494 r hor_cnt_reg[1]/Q net (fo=14, routed) 0.389 -0.104 hor_cnt_reg_n_0_[1] SLICE_X50Y54 LUT3 (Prop_lut3_I1_O) 0.099 -0.005 r hor_cnt[2]_i_1/O net (fo=1, routed) 0.000 -0.005 hor_cnt[2] SLICE_X50Y54 FDRE r hor_cnt_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X50Y54 FDRE r hor_cnt_reg[2]/C clock pessimism 0.502 -0.361 SLICE_X50Y54 FDRE (Hold_fdre_C_D) 0.120 -0.241 hor_cnt_reg[2] ------------------------------------------------------------------- required time 0.241 arrival time -0.005 ------------------------------------------------------------------- slack 0.236 Slack (MET) : 0.261ns (arrival time - required time) Source: hor_cnt_reg[9]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: hor_cnt_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.382ns (logic 0.209ns (54.690%) route 0.173ns (45.310%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.625ns Clock Pessimism Removal (CPR): -0.238ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.554 -0.625 clk_25MHz SLICE_X50Y53 FDRE r hor_cnt_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.461 r hor_cnt_reg[9]/Q net (fo=12, routed) 0.173 -0.287 hor_cnt_reg_n_0_[9] SLICE_X50Y53 LUT6 (Prop_lut6_I5_O) 0.045 -0.242 r hor_cnt[9]_i_1/O net (fo=1, routed) 0.000 -0.242 hor_cnt[9] SLICE_X50Y53 FDRE r hor_cnt_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X50Y53 FDRE r hor_cnt_reg[9]/C clock pessimism 0.238 -0.625 SLICE_X50Y53 FDRE (Hold_fdre_C_D) 0.121 -0.504 hor_cnt_reg[9] ------------------------------------------------------------------- required time 0.504 arrival time -0.242 ------------------------------------------------------------------- slack 0.261 Slack (MET) : 0.262ns (arrival time - required time) Source: ver_cnt_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[8]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.385ns (logic 0.190ns (49.396%) route 0.195ns (50.604%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.625ns Clock Pessimism Removal (CPR): -0.254ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.554 -0.625 clk_25MHz SLICE_X51Y54 FDRE r ver_cnt_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.484 r ver_cnt_reg[6]/Q net (fo=12, routed) 0.195 -0.289 ver_cnt_reg_n_0_[6] SLICE_X51Y55 LUT4 (Prop_lut4_I2_O) 0.049 -0.240 r ver_cnt[8]_i_1/O net (fo=1, routed) 0.000 -0.240 ver_cnt[8]_i_1_n_0 SLICE_X51Y55 FDRE r ver_cnt_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X51Y55 FDRE r ver_cnt_reg[8]/C clock pessimism 0.254 -0.609 SLICE_X51Y55 FDRE (Hold_fdre_C_D) 0.107 -0.502 ver_cnt_reg[8] ------------------------------------------------------------------- required time 0.502 arrival time -0.240 ------------------------------------------------------------------- slack 0.262 Slack (MET) : 0.271ns (arrival time - required time) Source: ver_cnt_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: ver_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by clk_out_clk_100to25MHz {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: clk_out_clk_100to25MHz Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_out_clk_100to25MHz rise@0.000ns - clk_out_clk_100to25MHz rise@0.000ns) Data Path Delay: 0.363ns (logic 0.186ns (51.283%) route 0.177ns (48.717%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.863ns Source Clock Delay (SCD): -0.625ns Clock Pessimism Removal (CPR): -0.238ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.258 0.258 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.698 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.421 -1.722 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.518 -1.204 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -1.178 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.554 -0.625 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y54 FDRE (Prop_fdre_C_Q) 0.141 -0.484 r ver_cnt_reg[1]/Q net (fo=21, routed) 0.177 -0.307 ver_cnt_reg_n_0_[1] SLICE_X53Y54 LUT6 (Prop_lut6_I2_O) 0.045 -0.262 r ver_cnt[0]_i_1/O net (fo=1, routed) 0.000 -0.262 ver_cnt[0]_i_1_n_0 SLICE_X53Y54 FDRE r ver_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk_out_clk_100to25MHz rise edge) 0.000 0.000 r Y9 0.000 0.000 r clk_100MHz (IN) net (fo=0) 0.000 0.000 clk_converter/inst/clk_in Y9 IBUF (Prop_ibuf_I_O) 0.446 0.446 r clk_converter/inst/clkin1_ibufg/O net (fo=1, routed) 0.480 0.926 clk_converter/inst/clk_in_clk_100to25MHz MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -3.204 -2.278 r clk_converter/inst/mmcm_adv_inst/CLKOUT0 net (fo=1, routed) 0.564 -1.714 clk_converter/inst/clk_out_clk_100to25MHz BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 -1.685 r clk_converter/inst/clkout1_buf/O net (fo=35, routed) 0.822 -0.863 clk_25MHz SLICE_X53Y54 FDRE r ver_cnt_reg[0]/C clock pessimism 0.238 -0.625 SLICE_X53Y54 FDRE (Hold_fdre_C_D) 0.092 -0.533 ver_cnt_reg[0] ------------------------------------------------------------------- required time 0.533 arrival time -0.262 ------------------------------------------------------------------- slack 0.271 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_out_clk_100to25MHz Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y1 clk_converter/inst/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X49Y53 Hsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X52Y55 Vsync_sig_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X53Y54 ver_cnt_reg[0]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X53Y54 ver_cnt_reg[1]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X53Y54 ver_cnt_reg[2]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X51Y55 ver_cnt_reg[3]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X50Y55 ver_cnt_reg[4]/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X53Y54 ver_cnt_reg[5]/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKOUT0 Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X49Y53 Hsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X48Y53 hor_cnt_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X48Y53 hor_cnt_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X52Y55 Vsync_sig_reg/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X53Y54 ver_cnt_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X53Y54 ver_cnt_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X53Y54 ver_cnt_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X51Y55 ver_cnt_reg[3]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X50Y55 ver_cnt_reg[4]/C Low Pulse Width Fast FDRE/C n/a 0.500 20.000 19.500 SLICE_X53Y54 ver_cnt_reg[5]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X49Y53 Hsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X52Y55 Vsync_sig_reg/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X53Y54 ver_cnt_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X53Y54 ver_cnt_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X53Y54 ver_cnt_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X51Y55 ver_cnt_reg[3]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X50Y55 ver_cnt_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X53Y54 ver_cnt_reg[5]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X51Y54 ver_cnt_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.500 20.000 19.500 SLICE_X51Y55 ver_cnt_reg[7]/C --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_100to25MHz To Clock: clkfbout_clk_100to25MHz Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_100to25MHz Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_converter/inst/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y2 clk_converter/inst/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X0Y0 clk_converter/inst/mmcm_adv_inst/CLKFBOUT