Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
| Date         : Wed Dec 13 11:59:01 2017
| Host         : VLSI-01 running 64-bit Ubuntu 14.04.5 LTS
| Command      : report_control_sets -verbose -file blockout_control_sets_placed.rpt
| Design       : blockout
| Device       : xc7z020
-------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |    10 |
| Unused register locations in slices containing registers |    41 |
+----------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             139 |           95 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              12 |            5 |
| Yes          | No                    | No                     |              62 |           20 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |               2 |            2 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+-----------------------------+----------------+-------------------+------------------+----------------+
|         Clock Signal        |  Enable Signal |  Set/Reset Signal | Slice Load Count | Bel Load Count |
+-----------------------------+----------------+-------------------+------------------+----------------+
|  clk_converter/inst/clk_out | Hsync_sig      | Hsync_sig_i_1_n_0 |                1 |              1 |
|  clk_converter/inst/clk_out | Vsync_sig      | Vsync_sig_i_1_n_0 |                1 |              1 |
|  clk_converter/inst/clk_out | ver_cnt        |                   |                4 |             10 |
|  clk_converter/inst/clk_out |                |                   |                5 |             11 |
|  clk_converter/inst/clk_out |                | video_sig         |                5 |             12 |
|  enable_reg_n_0_BUFG        | ball_vx        |                   |                4 |             13 |
|  enable_reg_n_0_BUFG        | ball_x_precise |                   |                4 |             13 |
|  enable_reg_n_0_BUFG        | ball_y_precise |                   |                4 |             13 |
|  enable_reg_n_0_BUFG        | ball_vy        |                   |                4 |             13 |
|  enable_reg_n_0_BUFG        |                |                   |               90 |            128 |
+-----------------------------+----------------+-------------------+------------------+----------------+


+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 1      |                     2 |
| 10     |                     1 |
| 11     |                     1 |
| 12     |                     1 |
| 13     |                     4 |
| 16+    |                     1 |
+--------+-----------------------+