#-----------------------------------------------------------
# Vivado v2016.4 (64-bit)
# SW Build 1733598 on Wed Dec 14 22:35:42 MST 2016
# IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
# Start of session at: Tue Dec  5 11:57:04 2017
# Process ID: 5844
# Current directory: /home/hakta/Documents/FPGA/blockout/blockout.runs/clk_wiz_0_synth_1
# Command line: vivado -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
# Log file: /home/hakta/Documents/FPGA/blockout/blockout.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
# Journal file: /home/hakta/Documents/FPGA/blockout/blockout.runs/clk_wiz_0_synth_1/vivado.jou
#-----------------------------------------------------------
source clk_wiz_0.tcl -notrace
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1084.977 ; gain = 157.082 ; free physical = 15578 ; free virtual = 17193
INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70]
INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:14146]
INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:14146]
INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:20414]
INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:20414]
INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/opt/Xilinx/Vivado/2016.4/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (5#1) [/home/hakta/Documents/FPGA/blockout/blockout.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70]
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1126.453 ; gain = 198.559 ; free physical = 15532 ; free virtual = 17150
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1126.453 ; gain = 198.559 ; free physical = 15532 ; free virtual = 17150
INFO: [Device 21-403] Loading part xc7z020clg484-1
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1388.266 ; gain = 0.000 ; free physical = 15342 ; free virtual = 16962
Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1388.266 ; gain = 460.371 ; free physical = 15339 ; free virtual = 16961
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1388.266 ; gain = 460.371 ; free physical = 15339 ; free virtual = 16961
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1388.266 ; gain = 460.371 ; free physical = 15339 ; free virtual = 16961
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1388.266 ; gain = 460.371 ; free physical = 15339 ; free virtual = 16960
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1388.266 ; gain = 460.371 ; free physical = 15339 ; free virtual = 16961
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1410.266 ; gain = 482.371 ; free physical = 15279 ; free virtual = 16901
Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1410.266 ; gain = 482.371 ; free physical = 15279 ; free virtual = 16901
Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1419.277 ; gain = 491.383 ; free physical = 15270 ; free virtual = 16892
Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1419.281 ; gain = 491.387 ; free physical = 15295 ; free virtual = 16917
Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1419.281 ; gain = 491.387 ; free physical = 15295 ; free virtual = 16917
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1419.281 ; gain = 491.387 ; free physical = 15295 ; free virtual = 16917
Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1419.281 ; gain = 491.387 ; free physical = 15295 ; free virtual = 16917
Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1419.281 ; gain = 491.387 ; free physical = 15295 ; free virtual = 16917
Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1419.281 ; gain = 491.387 ; free physical = 15295 ; free virtual = 16917

Report Cell Usage: 
+------+-----------+------+
|      |Cell       |Count |
+------+-----------+------+
|1     |BUFG       |     2|
|2     |MMCME2_ADV |     1|
|3     |IBUF       |     1|
+------+-----------+------+
Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1419.281 ; gain = 491.387 ; free physical = 15295 ; free virtual = 16917
synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1754.426 ; gain = 751.027 ; free physical = 14970 ; free virtual = 16592