Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (ISE) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx45
Project ID (random number) 8a4804c137c74cb293c76dbd3baed665.C1B791A318FA406E8B101B590A696DC4.4 Target Package: csg324
Registration ID 174113044_1777490152_210622501_804 Target Speed: -3
Date Generated 2016-04-14T19:59:19 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-4790 CPU @ 3.60GHz CPU Speed 3591 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-4790 CPU @ 3.60GHz CPU Speed 3591 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Xors=2
  • 1-bit xor2=2
 		MiscellaneousStatistics
  • AGG_BONDED_IO=5
  • AGG_IO=5
  • AGG_LOCED_IO=5
  • AGG_SLICE=1
  • NUM_BONDED_IOB=5
  • NUM_BSLUTONLY=1
  • NUM_BSUSED=1
  • NUM_LOCED_IOB=5
  • NUM_LOGIC_O5ANDO6=1
  • NUM_SLICEX=1
  • NUM_SLICE_CYINIT=2
  • NUM_SLICE_UNUSEDCTRL=1
 		NetStatistics
  • NumNets_Active=10
  • NumNets_Vcc=1
  • NumNodesOfType_Active_DOUBLE=6
  • NumNodesOfType_Active_GENERIC=8
  • NumNodesOfType_Active_IOBIN2OUT=5
  • NumNodesOfType_Active_IOBOUTPUT=5
  • NumNodesOfType_Active_LUTINPUT=3
  • NumNodesOfType_Active_OUTBOUND=8
  • NumNodesOfType_Active_OUTPUT=2
  • NumNodesOfType_Active_PADINPUT=2
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINFEED=5
  • NumNodesOfType_Active_QUAD=55
  • NumNodesOfType_Active_SINGLE=5
  • NumNodesOfType_Vcc_HVCCOUT=1
  • NumNodesOfType_Vcc_LUTINPUT=1
  • NumNodesOfType_Vcc_PINFEED=1
 SiteStatistics
  • IOB-IOBM=2
  • IOB-IOBS=3
  • SLICEX-SLICEL=1
 		SiteSummary
  • IOB=5
  • IOB_IMUX=3
  • IOB_INBUF=3
  • IOB_OUTBUF=2
  • LUT5=1
  • LUT6=1
  • PAD=5
  • SLICEX=1
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:2]
  • SLEW=[SLOW:2]
  • SUSPEND=[3STATE:2]
 
Pin Data
IOB
  • I=3
  • O=2
  • PAD=5
 IOB_IMUX
  • I=3
  • OUT=3
 IOB_INBUF
  • OUT=3
  • PAD=3
 IOB_OUTBUF
  • IN=2
  • OUT=2
 LUT5
  • A3=1
  • A4=1
  • A5=1
  • O5=1
 LUT6
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • O6=1
 PAD
  • PAD=5
 SLICEX
  • A=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • AMUX=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx45-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx45-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 3 3 0 0 0 0 0
map 6 6 0 0 0 0 0
ngdbuild 6 6 0 0 0 0 0
par 6 6 0 0 0 0 0
trce 6 6 0 0 0 0 0
xst 4 4 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/pn_db_nsw_select_source_type.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/full_adder_tb PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2016-04-14T19:25:04 PROP_intWbtProjectID=C1B791A318FA406E8B101B590A696DC4
PROP_intWbtProjectIteration=4 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.full_adder_tb PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx45
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=csg324
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=2
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_OBUF=2
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_LUT3=2 NGDBUILD_NUM_OBUF=2
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx45-3-csg324
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=342 ms, 30336 KB