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/4-szemeszter/DigSzAr/FPGA gyak/Full adder/

0 directories 14 files 1.6 MiB total
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Name
Size Modified
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full_adder.bit
1.4 MiB
full_adder.par
6.1 KiB
full_adder.syr
9.8 KiB
full_adder.ucf
115 B
full_adder.vhd
1.2 KiB
full_adder_envsettings.html
16 KiB
full_adder_map.map
5.9 KiB
full_adder_map.mrp
8.2 KiB
full_adder_pad.txt
64 KiB
full_adder_summary.html
13 KiB
full_adder_tb.vhd
2.5 KiB
par_usage_statistics.html
4.0 KiB
truth_table.txt
74 B
usage_statistics_webtalk.html
31 KiB